2015-03-12 12:24:39 +08:00
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CONFIG_ARM=y
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2019-05-03 21:41:00 +08:00
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CONFIG_SPL_SYS_DCACHE_OFF=y
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2015-03-16 15:43:24 +08:00
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CONFIG_ARCH_ZYNQ=y
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2016-12-16 18:57:17 +08:00
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CONFIG_SYS_TEXT_BASE=0x4000000
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2020-01-23 02:38:00 +08:00
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CONFIG_DM_GPIO=y
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2019-04-30 03:54:04 +08:00
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CONFIG_SPL_STACK_R_ADDR=0x200000
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2018-03-23 16:34:00 +08:00
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CONFIG_SPL=y
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2018-06-04 14:33:30 +08:00
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CONFIG_DEBUG_UART_BASE=0xe0001000
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CONFIG_DEBUG_UART_CLOCK=50000000
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2017-12-13 17:35:06 +08:00
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CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM010"
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2017-11-02 17:40:57 +08:00
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CONFIG_DEBUG_UART=y
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2018-01-10 02:31:16 +08:00
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CONFIG_DISTRO_DEFAULTS=y
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2019-06-02 20:57:32 +08:00
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CONFIG_SYS_CUSTOM_LDSCRIPT=y
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CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
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2015-01-23 18:31:53 +08:00
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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2017-01-21 18:48:33 +08:00
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CONFIG_FIT_VERBOSE=y
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2019-05-23 19:14:07 +08:00
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CONFIG_LEGACY_IMAGE_FORMAT=y
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2019-07-21 10:51:14 +08:00
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CONFIG_USE_PREBOOT=y
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2017-12-01 20:50:33 +08:00
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CONFIG_SPL_STACK_R=y
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2016-10-06 13:55:15 +08:00
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CONFIG_SPL_OS_BOOT=y
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2018-04-07 22:05:27 +08:00
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CONFIG_SPL_SPI_LOAD=y
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2019-08-22 21:41:46 +08:00
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
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2019-10-14 15:38:39 +08:00
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# CONFIG_BOOTM_NETBSD is not set
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2017-05-17 17:25:21 +08:00
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CONFIG_CMD_FPGA_LOADBP=y
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CONFIG_CMD_FPGA_LOADFS=y
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CONFIG_CMD_FPGA_LOADMK=y
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CONFIG_CMD_FPGA_LOADP=y
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2015-11-11 21:39:33 +08:00
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CONFIG_CMD_GPIO=y
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2017-08-15 07:58:53 +08:00
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CONFIG_CMD_MMC=y
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2015-06-23 05:15:30 +08:00
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# CONFIG_CMD_SETEXPR is not set
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2016-04-23 04:41:25 +08:00
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CONFIG_CMD_TFTPPUT=y
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2016-04-25 05:29:26 +08:00
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4_WRITE=y
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2018-02-11 05:54:38 +08:00
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# CONFIG_SPL_DOS_PARTITION is not set
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# CONFIG_SPL_EFI_PARTITION is not set
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2018-09-04 03:26:12 +08:00
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CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
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2017-08-28 19:16:32 +08:00
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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2019-11-13 11:46:36 +08:00
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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2015-07-17 19:26:06 +08:00
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CONFIG_NET_RANDOM_ETHADDR=y
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2016-01-08 01:00:46 +08:00
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CONFIG_SPL_DM_SEQ_ALIAS=y
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2017-11-03 22:53:56 +08:00
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CONFIG_FPGA_XILINX=y
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2018-02-16 20:32:51 +08:00
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CONFIG_FPGA_ZYNQPL=y
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2016-12-07 21:10:28 +08:00
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CONFIG_MMC_SDHCI=y
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2017-02-10 20:57:35 +08:00
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CONFIG_MMC_SDHCI_ZYNQ=y
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2019-02-27 22:20:36 +08:00
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CONFIG_SF_DEFAULT_SPEED=30000000
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2016-01-25 22:39:26 +08:00
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CONFIG_SPI_FLASH_ISSI=y
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2017-11-02 17:44:48 +08:00
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CONFIG_SPI_FLASH_MACRONIX=y
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2015-11-25 21:34:54 +08:00
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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2018-01-24 13:21:30 +08:00
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_XILINX=y
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2018-07-21 12:03:57 +08:00
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CONFIG_MII=y
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2015-11-30 21:34:52 +08:00
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CONFIG_ZYNQ_GEM=y
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2017-11-02 17:40:57 +08:00
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CONFIG_DEBUG_UART_ZYNQ=y
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2017-11-06 16:16:05 +08:00
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CONFIG_ZYNQ_SERIAL=y
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2015-11-25 21:34:53 +08:00
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CONFIG_ZYNQ_SPI=y
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2015-08-31 20:08:40 +08:00
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CONFIG_ZYNQ_QSPI=y
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