2018-05-07 05:58:06 +08:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2004-12-17 01:33:38 +08:00
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/*
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* (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
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*/
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#ifndef _universe_h
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#define _universe_h
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typedef struct _UNIVERSE UNIVERSE;
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typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
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typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
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struct _SLAVE_IMAGE {
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unsigned int ctl; /* Control */
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unsigned int bs; /* Base */
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unsigned int bd; /* Bound */
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unsigned int to; /* Translation */
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unsigned int reserved;
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};
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struct _UNIVERSE {
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unsigned int pci_id;
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unsigned int pci_csr;
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unsigned int pci_class;
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unsigned int pci_misc0;
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unsigned int pci_bs;
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unsigned int spare0[10];
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unsigned int pci_misc1;
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unsigned int spare1[48];
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SLAVE_IMAGE lsi[4];
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unsigned int spare2[8];
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unsigned int scyc_ctl;
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unsigned int scyc_addr;
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unsigned int scyc_en;
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unsigned int scyc_cmp;
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unsigned int scyc_swp;
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unsigned int lmisc;
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unsigned int slsi;
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unsigned int l_cmderr;
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unsigned int laerr;
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unsigned int spare3[27];
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unsigned int dctl;
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unsigned int dtbc;
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unsigned int dla;
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unsigned int spare4[1];
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unsigned int dva;
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unsigned int spare5[1];
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unsigned int dcpp;
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unsigned int spare6[1];
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unsigned int dgcs;
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unsigned int d_llue;
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unsigned int spare7[54];
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unsigned int lint_en;
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unsigned int lint_stat;
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unsigned int lint_map0;
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unsigned int lint_map1;
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unsigned int vint_en;
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unsigned int vint_stat;
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unsigned int vint_map0;
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unsigned int vint_map1;
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unsigned int statid;
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unsigned int vx_statid[7];
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unsigned int spare8[48];
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unsigned int mast_ctl;
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unsigned int misc_ctl;
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unsigned int misc_stat;
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unsigned int user_am;
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unsigned int spare9[700];
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SLAVE_IMAGE vsi[4];
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unsigned int spare10[8];
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unsigned int vrai_ctl;
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unsigned int vrai_bs;
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unsigned int spare11[2];
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unsigned int vcsr_ctl;
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unsigned int vcsr_to;
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unsigned int v_amerr;
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unsigned int vaerr;
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unsigned int spare12[25];
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unsigned int vcsr_clr;
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unsigned int vcsr_set;
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unsigned int vcsr_bs;
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};
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#define IRQ_VOWN 0x0001
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#define IRQ_VIRQ1 0x0002
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#define IRQ_VIRQ2 0x0004
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#define IRQ_VIRQ3 0x0008
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#define IRQ_VIRQ4 0x0010
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#define IRQ_VIRQ5 0x0020
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#define IRQ_VIRQ6 0x0040
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#define IRQ_VIRQ7 0x0080
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#define IRQ_DMA 0x0100
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#define IRQ_LERR 0x0200
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#define IRQ_VERR 0x0400
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#define IRQ_res 0x0800
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#define IRQ_IACK 0x1000
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#define IRQ_SWINT 0x2000
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#define IRQ_SYSFAIL 0x4000
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#define IRQ_ACFAIL 0x8000
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struct _TDMA_CMD_PACKET {
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unsigned int dctl; /* DMA Control */
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unsigned int dtbc; /* Transfer Byte Count */
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unsigned int dlv; /* PCI Address */
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unsigned int res1; /* Reserved */
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unsigned int dva; /* Vme Address */
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unsigned int res2; /* Reserved */
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unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
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unsigned int res3; /* Reserved */
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};
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#define VME_AM_A16 0x01
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#define VME_AM_A24 0x02
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#define VME_AM_A32 0x03
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#define VME_AM_Axx 0x03
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#define VME_AM_SUP 0x04
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#define VME_AM_DATA 0x10
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#define VME_AM_PROG 0x20
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#define VME_AM_Mxx 0x30
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#define VME_FLAG_D8 0x01
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#define VME_FLAG_D16 0x02
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#define VME_FLAG_D32 0x03
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#define VME_FLAG_Dxx 0x03
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#define PCI_MS_MEM 0x01
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#define PCI_MS_IO 0x02
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#define PCI_MS_CONFIG 0x03
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#define PCI_MS_Mxx 0x03
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#endif
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