mirror of
https://github.com/linux-sunxi/sunxi-tools.git
synced 2024-11-27 03:44:22 +08:00
607 lines
18 KiB
C
607 lines
18 KiB
C
/*
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* (C) Copyright 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "fel_lib.h"
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#include "progress.h"
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#include "fel-remotefunc-spi-data-transfer.h"
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/*****************************************************************************/
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typedef struct {
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uint32_t id;
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uint8_t write_enable_cmd;
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uint8_t large_erase_cmd;
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uint32_t large_erase_size;
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uint8_t small_erase_cmd;
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uint32_t small_erase_size;
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uint8_t program_cmd;
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uint32_t program_size;
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char *text_description;
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} spi_flash_info_t;
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spi_flash_info_t spi_flash_info[] = {
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{ .id = 0xEF40, .write_enable_cmd = 0x6,
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.large_erase_cmd = 0xD8, .large_erase_size = 64 * 1024,
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.small_erase_cmd = 0x20, .small_erase_size = 4 * 1024,
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.program_cmd = 0x02, .program_size = 256,
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.text_description = "Winbond W25Qxx" },
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{ .id = 0xC220, .write_enable_cmd = 0x6,
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.large_erase_cmd = 0xD8, .large_erase_size = 64 * 1024,
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.small_erase_cmd = 0x20, .small_erase_size = 4 * 1024,
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.program_cmd = 0x02, .program_size = 256,
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.text_description = "Macronix MX25Lxxxx" },
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{ .id = 0x1C70, .write_enable_cmd = 0x6,
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.large_erase_cmd = 0xD8, .large_erase_size = 64 * 1024,
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.small_erase_cmd = 0x20, .small_erase_size = 4 * 1024,
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.program_cmd = 0x02, .program_size = 256,
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.text_description = "Eon EN25QHxx" },
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};
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spi_flash_info_t default_spi_flash_info = {
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.id = 0x0000, .write_enable_cmd = 0x6,
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.large_erase_cmd = 0xD8, .large_erase_size = 64 * 1024,
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.small_erase_cmd = 0x20, .small_erase_size = 4 * 1024,
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.program_cmd = 0x02, .program_size = 256,
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.text_description = "Unknown",
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};
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/*****************************************************************************/
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uint32_t fel_readl(feldev_handle *dev, uint32_t addr);
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void fel_writel(feldev_handle *dev, uint32_t addr, uint32_t val);
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#define readl(addr) fel_readl(dev, (addr))
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#define writel(val, addr) fel_writel(dev, (addr), (val))
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#define PA (0)
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#define PB (1)
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#define PC (2)
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#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
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#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
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#define CCM_AHB_GATE_SPI0 (1 << 20)
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#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
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#define SUN6I_SPI0_RST (1 << 20)
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#define SUNIV_PLL6_CTL (0x01c20000 + 0x28)
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#define SUNIV_AHB_APB_CFG (0x01c20000 + 0x54)
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#define H6_CCM_SPI0_CLK (0x03001000 + 0x940)
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#define H6_CCM_SPI_BGR (0x03001000 + 0x96C)
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#define H6_CCM_SPI0_GATE_RESET (1 << 0 | 1 << 16)
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#define SUNIV_GPC_SPI0 (2)
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#define SUNXI_GPC_SPI0 (3)
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#define SUN50I_GPC_SPI0 (4)
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#define SUN4I_CTL_ENABLE (1 << 0)
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#define SUN4I_CTL_MASTER (1 << 1)
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#define SUN4I_CTL_TF_RST (1 << 8)
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#define SUN4I_CTL_RF_RST (1 << 9)
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#define SUN4I_CTL_XCH (1 << 10)
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#define SUN6I_TCR_XCH (1U << 31)
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#define SUN4I_SPI0_CCTL (spi_base(dev) + 0x1C)
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#define SUN4I_SPI0_CTL (spi_base(dev) + 0x08)
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#define SUN4I_SPI0_RX (spi_base(dev) + 0x00)
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#define SUN4I_SPI0_TX (spi_base(dev) + 0x04)
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#define SUN4I_SPI0_FIFO_STA (spi_base(dev) + 0x28)
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#define SUN4I_SPI0_BC (spi_base(dev) + 0x20)
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#define SUN4I_SPI0_TC (spi_base(dev) + 0x24)
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#define SUN6I_SPI0_CCTL (spi_base(dev) + 0x24)
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#define SUN6I_SPI0_GCR (spi_base(dev) + 0x04)
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#define SUN6I_SPI0_TCR (spi_base(dev) + 0x08)
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#define SUN6I_SPI0_FIFO_STA (spi_base(dev) + 0x1C)
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#define SUN6I_SPI0_MBC (spi_base(dev) + 0x30)
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#define SUN6I_SPI0_MTC (spi_base(dev) + 0x34)
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#define SUN6I_SPI0_BCC (spi_base(dev) + 0x38)
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#define SUN6I_SPI0_TXD (spi_base(dev) + 0x200)
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#define SUN6I_SPI0_RXD (spi_base(dev) + 0x300)
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#define CCM_SPI0_CLK_DIV_BY_2 (0x1000)
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#define CCM_SPI0_CLK_DIV_BY_4 (0x1001)
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#define CCM_SPI0_CLK_DIV_BY_6 (0x1002)
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#define CCM_SPI0_CLK_DIV_BY_32 (0x100f)
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static uint32_t gpio_base(feldev_handle *dev)
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{
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soc_info_t *soc_info = dev->soc_info;
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switch (soc_info->soc_id) {
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case 0x1816: /* V536 */
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case 0x1817: /* V831 */
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case 0x1728: /* H6 */
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case 0x1823: /* H616 */
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return 0x0300B000;
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default:
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return 0x01C20800;
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}
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}
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static uint32_t spi_base(feldev_handle *dev)
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{
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soc_info_t *soc_info = dev->soc_info;
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switch (soc_info->soc_id) {
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case 0x1623: /* A10 */
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case 0x1625: /* A13 */
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case 0x1651: /* A20 */
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case 0x1663: /* F1C100s */
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case 0x1701: /* R40 */
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return 0x01C05000;
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case 0x1816: /* V536 */
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case 0x1817: /* V831 */
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case 0x1728: /* H6 */
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case 0x1823: /* H616 */
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return 0x05010000;
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default:
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return 0x01C68000;
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}
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}
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/*
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* Configure pin function on a GPIO port
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*/
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static void gpio_set_cfgpin(feldev_handle *dev, int port_num, int pin_num,
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int val)
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{
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uint32_t port_base = gpio_base(dev) + port_num * 0x24;
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uint32_t cfg_reg = port_base + 4 * (pin_num / 8);
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uint32_t pin_idx = pin_num % 8;
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uint32_t x = readl(cfg_reg);
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x &= ~(0x7 << (pin_idx * 4));
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x |= val << (pin_idx * 4);
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writel(x, cfg_reg);
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}
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static bool spi_is_sun6i(feldev_handle *dev)
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{
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soc_info_t *soc_info = dev->soc_info;
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switch (soc_info->soc_id) {
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case 0x1623: /* A10 */
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case 0x1625: /* A13 */
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case 0x1651: /* A20 */
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return false;
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default:
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return true;
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}
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}
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static bool soc_is_h6_style(feldev_handle *dev)
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{
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soc_info_t *soc_info = dev->soc_info;
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switch (soc_info->soc_id) {
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case 0x1816: /* V536 */
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case 0x1817: /* V831 */
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case 0x1728: /* H6 */
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case 0x1823: /* H616 */
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return true;
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default:
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return false;
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}
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}
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/*
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* Init the SPI0 controller and setup pins muxing.
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*/
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static bool spi0_init(feldev_handle *dev)
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{
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uint32_t reg_val;
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soc_info_t *soc_info = dev->soc_info;
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if (!soc_info) {
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printf("Unable to fetch device information. "
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"Possibly unknown device.\n");
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return false;
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}
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/* Setup SPI0 pins muxing */
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switch (soc_info->soc_id) {
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case 0x1663: /* Allwinner F1C100s/F1C600/R6/F1C100A/F1C500 */
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gpio_set_cfgpin(dev, PC, 0, SUNIV_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 1, SUNIV_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 2, SUNIV_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 3, SUNIV_GPC_SPI0);
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break;
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case 0x1625: /* Allwinner A13 */
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case 0x1680: /* Allwinner H3 */
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case 0x1681: /* Allwinner V3s */
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case 0x1718: /* Allwinner H5 */
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gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 3, SUNXI_GPC_SPI0);
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break;
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case 0x1623: /* Allwinner A10 */
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case 0x1651: /* Allwinner A20 */
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case 0x1701: /* Allwinner R40 */
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gpio_set_cfgpin(dev, PC, 0, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 1, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 2, SUNXI_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 23, SUNXI_GPC_SPI0);
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break;
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case 0x1689: /* Allwinner A64 */
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gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 2, SUN50I_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0);
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break;
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case 0x1816: /* Allwinner V536 */
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case 0x1817: /* Allwinner V831 */
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gpio_set_cfgpin(dev, PC, 1, SUN50I_GPC_SPI0); /* SPI0-CS */
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/* fall-through */
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case 0x1728: /* Allwinner H6 */
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gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 2, SUN50I_GPC_SPI0);
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gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0);
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/* PC5 is SPI0-CS on the H6, and SPI0-HOLD on the V831 */
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gpio_set_cfgpin(dev, PC, 5, SUN50I_GPC_SPI0);
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break;
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case 0x1823: /* Allwinner H616 */
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gpio_set_cfgpin(dev, PC, 0, SUN50I_GPC_SPI0); /* SPI0_CLK */
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gpio_set_cfgpin(dev, PC, 2, SUN50I_GPC_SPI0); /* SPI0_MOSI */
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gpio_set_cfgpin(dev, PC, 3, SUN50I_GPC_SPI0); /* SPI0_CS0 */
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gpio_set_cfgpin(dev, PC, 4, SUN50I_GPC_SPI0); /* SPI0_MISO */
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break;
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default: /* Unknown/Unsupported SoC */
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printf("SPI support not implemented yet for %x (%s)!\n",
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soc_info->soc_id, soc_info->name);
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return false;
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}
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if (soc_is_h6_style(dev)) {
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reg_val = readl(H6_CCM_SPI_BGR);
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reg_val |= H6_CCM_SPI0_GATE_RESET;
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writel(reg_val, H6_CCM_SPI_BGR);
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} else {
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if (spi_is_sun6i(dev)) {
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/* Deassert SPI0 reset */
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reg_val = readl(SUN6I_BUS_SOFT_RST_REG0);
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reg_val |= SUN6I_SPI0_RST;
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writel(reg_val, SUN6I_BUS_SOFT_RST_REG0);
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}
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reg_val = readl(CCM_AHB_GATING0);
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reg_val |= CCM_AHB_GATE_SPI0;
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writel(reg_val, CCM_AHB_GATING0);
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}
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if (soc_info->soc_id == 0x1663) { /* suniv F1C100s */
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/*
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* suniv doesn't have a module clock for SPI0 and the clock
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* source is always the AHB clock. Setup AHB to 200 MHz by
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* setting PLL6 to 600 MHz with a divider of 3, then program
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* the internal SPI dividier to 32.
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*/
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/* Set PLL6 to 600MHz */
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writel(0x80041801, SUNIV_PLL6_CTL);
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/* PLL6:AHB:APB = 6:2:1 */
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writel(0x00003180, SUNIV_AHB_APB_CFG);
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/* divide by 32 */
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writel(CCM_SPI0_CLK_DIV_BY_32, SUN6I_SPI0_CCTL);
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} else {
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/* divide 24MHz OSC by 4 */
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writel(CCM_SPI0_CLK_DIV_BY_4,
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spi_is_sun6i(dev) ? SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);
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/* Choose 24MHz from OSC24M and enable clock */
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writel(1U << 31,
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soc_is_h6_style(dev) ? H6_CCM_SPI0_CLK : CCM_SPI0_CLK);
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}
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if (spi_is_sun6i(dev)) {
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/* Enable SPI in the master mode and do a soft reset */
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reg_val = readl(SUN6I_SPI0_GCR);
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reg_val |= (1U << 31) | 3;
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writel(reg_val, SUN6I_SPI0_GCR);
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/* Wait for completion */
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while (readl(SUN6I_SPI0_GCR) & (1U << 31)) {}
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} else {
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reg_val = readl(SUN4I_SPI0_CTL);
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reg_val |= SUN4I_CTL_MASTER;
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reg_val |= SUN4I_CTL_ENABLE | SUN4I_CTL_TF_RST | SUN4I_CTL_RF_RST;
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writel(reg_val, SUN4I_SPI0_CTL);
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}
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return true;
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}
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/*
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* Backup/restore the initial portion of the SRAM, which can be used as
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* a temporary data buffer.
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*/
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static void *backup_sram(feldev_handle *dev)
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{
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soc_info_t *soc_info = dev->soc_info;
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size_t bufsize = soc_info->scratch_addr - soc_info->spl_addr;
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void *buf = malloc(bufsize);
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aw_fel_read(dev, soc_info->spl_addr, buf, bufsize);
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return buf;
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}
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static void restore_sram(feldev_handle *dev, void *buf)
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{
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soc_info_t *soc_info = dev->soc_info;
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size_t bufsize = soc_info->scratch_addr - soc_info->spl_addr;
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aw_fel_write(dev, buf, soc_info->spl_addr, bufsize);
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free(buf);
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}
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static void prepare_spi_batch_data_transfer(feldev_handle *dev, uint32_t buf)
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{
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if (spi_is_sun6i(dev)) {
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aw_fel_remotefunc_prepare_spi_batch_data_transfer(dev,
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buf,
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SUN6I_SPI0_TCR,
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SUN6I_TCR_XCH,
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SUN6I_SPI0_FIFO_STA,
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SUN6I_SPI0_TXD,
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SUN6I_SPI0_RXD,
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SUN6I_SPI0_MBC,
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SUN6I_SPI0_MTC,
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SUN6I_SPI0_BCC);
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} else {
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aw_fel_remotefunc_prepare_spi_batch_data_transfer(dev,
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buf,
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SUN4I_SPI0_CTL,
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SUN4I_CTL_XCH,
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SUN4I_SPI0_FIFO_STA,
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SUN4I_SPI0_TX,
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SUN4I_SPI0_RX,
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SUN4I_SPI0_BC,
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SUN4I_SPI0_TC,
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0);
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}
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}
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/*
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* Read data from the SPI flash. Use the first 4KiB of SRAM as the data buffer.
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*/
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void aw_fel_spiflash_read(feldev_handle *dev,
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uint32_t offset, void *buf, size_t len,
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progress_cb_t progress)
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{
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soc_info_t *soc_info = dev->soc_info;
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void *backup = backup_sram(dev);
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uint8_t *buf8 = (uint8_t *)buf;
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size_t max_chunk_size = soc_info->scratch_addr - soc_info->spl_addr;
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if (max_chunk_size > 0x1000)
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max_chunk_size = 0x1000;
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uint8_t *cmdbuf = malloc(max_chunk_size);
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memset(cmdbuf, 0, max_chunk_size);
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aw_fel_write(dev, cmdbuf, soc_info->spl_addr, max_chunk_size);
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if (!spi0_init(dev))
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return;
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prepare_spi_batch_data_transfer(dev, soc_info->spl_addr);
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progress_start(progress, len);
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while (len > 0) {
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size_t chunk_size = len;
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if (chunk_size > max_chunk_size - 8)
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chunk_size = max_chunk_size - 8;
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memset(cmdbuf, 0, max_chunk_size);
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cmdbuf[0] = (chunk_size + 4) >> 8;
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cmdbuf[1] = (chunk_size + 4);
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cmdbuf[2] = 3;
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cmdbuf[3] = offset >> 16;
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cmdbuf[4] = offset >> 8;
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cmdbuf[5] = offset;
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if (chunk_size == max_chunk_size - 8)
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aw_fel_write(dev, cmdbuf, soc_info->spl_addr, 6);
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else
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aw_fel_write(dev, cmdbuf, soc_info->spl_addr, chunk_size + 8);
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aw_fel_remotefunc_execute(dev, NULL);
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aw_fel_read(dev, soc_info->spl_addr + 6, buf8, chunk_size);
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len -= chunk_size;
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offset += chunk_size;
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|
buf8 += chunk_size;
|
|
progress_update(chunk_size);
|
|
}
|
|
|
|
free(cmdbuf);
|
|
restore_sram(dev, backup);
|
|
}
|
|
|
|
/*
|
|
* Write data to the SPI flash. Use the first 4KiB of SRAM as the data buffer.
|
|
*/
|
|
|
|
#define CMD_WRITE_ENABLE 0x06
|
|
|
|
void aw_fel_spiflash_write_helper(feldev_handle *dev,
|
|
uint32_t offset, void *buf, size_t len,
|
|
size_t erase_size, uint8_t erase_cmd,
|
|
size_t program_size, uint8_t program_cmd)
|
|
{
|
|
soc_info_t *soc_info = dev->soc_info;
|
|
uint8_t *buf8 = (uint8_t *)buf;
|
|
size_t max_chunk_size = soc_info->scratch_addr - soc_info->spl_addr;
|
|
size_t cmd_idx;
|
|
|
|
if (max_chunk_size > 0x1000)
|
|
max_chunk_size = 0x1000;
|
|
uint8_t *cmdbuf = malloc(max_chunk_size);
|
|
cmd_idx = 0;
|
|
|
|
prepare_spi_batch_data_transfer(dev, soc_info->spl_addr);
|
|
|
|
while (len > 0) {
|
|
while (len > 0 && max_chunk_size - cmd_idx > program_size + 64) {
|
|
if (offset % erase_size == 0) {
|
|
/* Emit write enable command */
|
|
cmdbuf[cmd_idx++] = 0;
|
|
cmdbuf[cmd_idx++] = 1;
|
|
cmdbuf[cmd_idx++] = CMD_WRITE_ENABLE;
|
|
/* Emit erase command */
|
|
cmdbuf[cmd_idx++] = 0;
|
|
cmdbuf[cmd_idx++] = 4;
|
|
cmdbuf[cmd_idx++] = erase_cmd;
|
|
cmdbuf[cmd_idx++] = offset >> 16;
|
|
cmdbuf[cmd_idx++] = offset >> 8;
|
|
cmdbuf[cmd_idx++] = offset;
|
|
/* Emit wait for completion */
|
|
cmdbuf[cmd_idx++] = 0xFF;
|
|
cmdbuf[cmd_idx++] = 0xFF;
|
|
}
|
|
/* Emit write enable command */
|
|
cmdbuf[cmd_idx++] = 0;
|
|
cmdbuf[cmd_idx++] = 1;
|
|
cmdbuf[cmd_idx++] = CMD_WRITE_ENABLE;
|
|
/* Emit page program command */
|
|
size_t write_count = program_size;
|
|
if (write_count > len)
|
|
write_count = len;
|
|
cmdbuf[cmd_idx++] = (4 + write_count) >> 8;
|
|
cmdbuf[cmd_idx++] = 4 + write_count;
|
|
cmdbuf[cmd_idx++] = program_cmd;
|
|
cmdbuf[cmd_idx++] = offset >> 16;
|
|
cmdbuf[cmd_idx++] = offset >> 8;
|
|
cmdbuf[cmd_idx++] = offset;
|
|
memcpy(cmdbuf + cmd_idx, buf8, write_count);
|
|
cmd_idx += write_count;
|
|
buf8 += write_count;
|
|
len -= write_count;
|
|
offset += write_count;
|
|
/* Emit wait for completion */
|
|
cmdbuf[cmd_idx++] = 0xFF;
|
|
cmdbuf[cmd_idx++] = 0xFF;
|
|
}
|
|
/* Emit the end marker */
|
|
cmdbuf[cmd_idx++] = 0;
|
|
cmdbuf[cmd_idx++] = 0;
|
|
|
|
/* Flush */
|
|
aw_fel_write(dev, cmdbuf, soc_info->spl_addr, cmd_idx);
|
|
aw_fel_remotefunc_execute(dev, NULL);
|
|
cmd_idx = 0;
|
|
}
|
|
|
|
free(cmdbuf);
|
|
}
|
|
|
|
void aw_fel_spiflash_write(feldev_handle *dev,
|
|
uint32_t offset, void *buf, size_t len,
|
|
progress_cb_t progress)
|
|
{
|
|
void *backup = backup_sram(dev);
|
|
uint8_t *buf8 = (uint8_t *)buf;
|
|
|
|
spi_flash_info_t *flash_info = &default_spi_flash_info; /* FIXME */
|
|
|
|
if ((offset % flash_info->small_erase_size) != 0) {
|
|
fprintf(stderr, "aw_fel_spiflash_write: 'addr' must be %d bytes aligned\n",
|
|
flash_info->small_erase_size);
|
|
exit(1);
|
|
}
|
|
|
|
if (!spi0_init(dev))
|
|
return;
|
|
|
|
progress_start(progress, len);
|
|
while (len > 0) {
|
|
size_t write_count;
|
|
if ((offset % flash_info->large_erase_size) != 0 ||
|
|
len < flash_info->large_erase_size) {
|
|
|
|
write_count = flash_info->small_erase_size;
|
|
if (write_count > len)
|
|
write_count = len;
|
|
aw_fel_spiflash_write_helper(dev, offset, buf8,
|
|
write_count,
|
|
flash_info->small_erase_size, flash_info->small_erase_cmd,
|
|
flash_info->program_size, flash_info->program_cmd);
|
|
} else {
|
|
write_count = flash_info->large_erase_size;
|
|
if (write_count > len)
|
|
write_count = len;
|
|
aw_fel_spiflash_write_helper(dev, offset, buf8,
|
|
write_count,
|
|
flash_info->large_erase_size, flash_info->large_erase_cmd,
|
|
flash_info->program_size, flash_info->program_cmd);
|
|
}
|
|
|
|
len -= write_count;
|
|
offset += write_count;
|
|
buf8 += write_count;
|
|
progress_update(write_count);
|
|
}
|
|
|
|
restore_sram(dev, backup);
|
|
}
|
|
|
|
/*
|
|
* Use the read JEDEC ID (9Fh) command.
|
|
*/
|
|
void aw_fel_spiflash_info(feldev_handle *dev)
|
|
{
|
|
soc_info_t *soc_info = dev->soc_info;
|
|
const char *manufacturer;
|
|
unsigned char buf[] = { 0, 4, 0x9F, 0, 0, 0, 0x0, 0x0 };
|
|
void *backup = backup_sram(dev);
|
|
|
|
if (!spi0_init(dev))
|
|
return;
|
|
|
|
aw_fel_write(dev, buf, soc_info->spl_addr, sizeof(buf));
|
|
prepare_spi_batch_data_transfer(dev, soc_info->spl_addr);
|
|
aw_fel_remotefunc_execute(dev, NULL);
|
|
aw_fel_read(dev, soc_info->spl_addr, buf, sizeof(buf));
|
|
|
|
restore_sram(dev, backup);
|
|
|
|
/* Assume that the MISO pin is either pulled up or down */
|
|
if (buf[5] == 0x00 || buf[5] == 0xFF) {
|
|
printf("No SPI flash detected.\n");
|
|
return;
|
|
}
|
|
|
|
switch (buf[3]) {
|
|
case 0xEF:
|
|
manufacturer = "Winbond";
|
|
break;
|
|
case 0xC2:
|
|
manufacturer = "Macronix";
|
|
break;
|
|
case 0x1C:
|
|
manufacturer = "Eon";
|
|
break;
|
|
default:
|
|
manufacturer = "Unknown";
|
|
break;
|
|
}
|
|
|
|
printf("Manufacturer: %s (%02Xh), model: %02Xh, size: %d bytes.\n",
|
|
manufacturer, buf[3], buf[4], (1U << buf[5]));
|
|
}
|
|
|
|
/*
|
|
* Show a help message about the available "spiflash-*" commands.
|
|
*/
|
|
void aw_fel_spiflash_help(void)
|
|
{
|
|
printf(" spiflash-info Retrieves basic information\n"
|
|
" spiflash-read addr length file Write SPI flash contents into file\n"
|
|
" spiflash-write addr file Store file contents into SPI flash\n");
|
|
}
|