To workaround a hardware erratum on the H3 SoC, we use an MMIO register
based assembly routine to dump the SID registers, if needed. This is
hard-coded to read the first four 32-bit words of the SID fuses.
For the sid-dump command we need to access any arbitrary regions of the
fuses, so extend the routine to take a start and an end address to dump.
This changes the assembly source in the thunks/ directory:
- We load the start address into r1, instead of zeroing it. The start
address is put right after the SIO MMIO base address, at the end of
the code.
- When storing the read value into the result buffer, we automatically
increase the pointer register (r3), instead of adding the offset
address, since this is now no longer zero based.
- To check for the end, we read the end pointer (stored at the end of
the code, right after the offset), and compare against that instead of
the hardcoded value of 16.
This assembly file was put through the thunks Makefile, and the resulting
content was copied from thunks/sid_read_root.h into fel_lib.c.
For now we are still putting the constant values of 0 and 16 in, but
this time from the C code.
Signed-off-by: Andre Przywara <osp@andrep.de>
Almost all thunks are already ARMv5 safe, so we can just require this
architecture on the gas command line, to enforce compatibility with the
F1Cx00 series. This prevents accidental changes in the future.
The RMR thunk uses the ARMv7 only DSB/ISB instructions, but this runs on
ARMv8 cores only anyway, so we just force ARMv7 for this file, and avoid
code changes.
Signed-off-by: Andre Przywara <osp@andrep.de>
Currently the thunk we upload into the SRAM is using DSB and ISB
instructions, which were introduced in ARMv7. Also it relies on
movw/movt pairs, which became available in ARMv6T2.
The Allwinner F1Cx00 SoCs are using an ARMv5TE compliant core, so they
do not know these instructions.
Change the code to be ARMv5TE compliant, so it can run on all relevant
Allwinner ARM cores:
- One movw is just used to compare two bits, replace that with a
tst/tsteq sequence to skip the load.
- The other movw/movt pairs get replaced with ldr's, that load from
literal storage at the end of the code (from Icenowy).
- The DSB and ISB get replaced with their CP15 MCR counterparts. Those
are deprecated in ARMv7, but still work, when the CP15BEN bit is set
in SCTLR. We check for this in fel.c (from Icenowy). ISB is not
implemented on the ARM926, so make this conditional. A simple branch
takes care of the desired pipeline flush for the old SoC.
Also remove the rather pointless Ruby prolog that generates the header
file. We have a less awkward version of this in the Makefile, and need
that for the other thunks there anyway, so it's just duplicated code.
Embedding a header generator in Ruby in an assembly file is a cute
gimmick, but serves no purpose anymore.
This is based on work by Icenowy, who put a similar solution in a
separate file.
Originally-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>
This patch moves the scan for an ARM gcc into a separate shell
script. To prevent against recursion issues, the new script adds
"-maxdepth 1" to the find invocation; and it now also correctly
handles directories in $PATH that contain spaces in their name.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
This function provides bitwise clear/set operations on 32-bit words
via FEL. It may help with implementing future functionality, where
ARM register manipulations often involve such bit level access.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
"make headers" (which in turn invokes "make -C thunks/" should now
build the include files via awk, avoiding the need for ruby.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
