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this is also very wrong
This commit is contained in:
Justin Miller
parent
e605673e2d
commit
0d5ce3da79
@ -27,6 +27,8 @@
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#include <internal/mips/ke.h>
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#elif defined(_M_ARM)
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#include <internal/arm/ke.h>
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#elif defined(_M_ARM64)
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#include <internal/arm64/ke.h>
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#elif defined(_M_AMD64)
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#include <internal/amd64/ke.h>
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#else
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@ -27,6 +27,8 @@
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#include <internal/mips/mm.h>
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#elif defined(_M_ARM)
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#include <internal/arm/mm.h>
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#elif defined(_M_ARM64)
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#include <internal/arm64/mm.h>
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#elif defined(_M_AMD64)
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#include <internal/amd64/mm.h>
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#else
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71
ntoskrnl/include/internal/arm64/ke.h
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71
ntoskrnl/include/internal/arm64/ke.h
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@ -0,0 +1,71 @@
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#pragma once
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#define KiServiceExit2 KiExceptionExit
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#define SYNCH_LEVEL DISPATCH_LEVEL
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#define PCR ((KPCR * const)KIP0PCRADDRESS)
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//
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//Lockdown TLB entries
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//
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#define PCR_ENTRY 0
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#define PDR_ENTRY 2
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//
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// BKPT is 4 bytes long
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//
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#define KD_BREAKPOINT_TYPE ULONG
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#define KD_BREAKPOINT_SIZE sizeof(ULONG)
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#define KD_BREAKPOINT_VALUE 0xDEFE
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//
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// Maximum IRQs
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//
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#define MAXIMUM_VECTOR 16
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//
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// Macros for getting and setting special purpose registers in portable code
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//
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#define KeGetContextPc(Context) \
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((Context)->Pc)
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#define KeSetContextPc(Context, ProgramCounter) \
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((Context)->Pc = (ProgramCounter))
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#define KeGetTrapFramePc(TrapFrame) \
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((TrapFrame)->Pc)
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#define KeGetContextReturnRegister(Context) \
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((Context)->R0)
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#define KeSetContextReturnRegister(Context, ReturnValue) \
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((Context)->R0 = (ReturnValue))
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//
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// Macro to get trap and exception frame from a thread stack
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//
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#define KeGetTrapFrame(Thread) \
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(PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
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sizeof(KTRAP_FRAME))
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#define KeGetExceptionFrame(Thread) \
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(PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
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sizeof(KEXCEPTION_FRAME))
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//
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// Macro to get context switches from the PRCB
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// All architectures but x86 have it in the PRCB's KeContextSwitches
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//
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#define KeGetContextSwitches(Prcb) \
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(Prcb)->KeContextSwitches
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//
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// Macro to get the second level cache size field name which differs between
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// CISC and RISC architectures, as the former has unified I/D cache
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//
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#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
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//
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// Returns the Interrupt State from a Trap Frame.
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// ON = TRUE, OFF = FALSE
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//
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#define KeGetTrapFrameInterruptState(TrapFrame) 0
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87
ntoskrnl/include/internal/arm64/mm.h
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87
ntoskrnl/include/internal/arm64/mm.h
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@ -0,0 +1,87 @@
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#pragma once
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#define _MI_PAGING_LEVELS 4
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#define _MI_HAS_NO_EXECUTE 1
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/* Memory layout base addresses (This is based on Vista!) */
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#define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
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#define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
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#define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
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//#define MI_PAGE_TABLE_BASE 0xFFFFF68000000000ULL // 512 GB page tables
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#define HYPER_SPACE 0xFFFFF70000000000ULL // 512 GB hyper space [MiVaProcessSpace]
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#define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
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//#define MI_SHARED_SYSTEM_PAGE 0xFFFFF78000000000ULL
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#define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL // 512 GB - 4 KB system cache working set
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//#define MI_LOADER_MAPPINGS 0xFFFFF80000000000ULL // 512 GB loader mappings aka KSEG0_BASE (NDK) [MiVaBootLoaded]
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#define MM_SYSTEM_SPACE_START 0xFFFFF88000000000ULL // 128 GB system PTEs [MiVaSystemPtes]
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#define MI_DEBUG_MAPPING (PVOID)0xFFFFF89FFFFFF000ULL // FIXME should be allocated from System PTEs
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#define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL // 128 GB paged pool [MiVaPagedPool]
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//#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL
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//#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL // 512 GB session space [MiVaSessionSpace]
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//#define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
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#define MI_SESSION_SPACE_END 0xFFFFF98000000000ULL
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#define MI_SYSTEM_CACHE_START 0xFFFFF98000000000ULL // 1 TB system cache (on Vista+ this is dynamic VA space) [MiVaSystemCache,MiVaSpecialPoolPaged,MiVaSpecialPoolNonPaged]
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#define MI_SYSTEM_CACHE_END 0xFFFFFA7FFFFFFFFFULL
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#define MI_PFN_DATABASE 0xFFFFFA8000000000ULL // up to 5.5 TB PFN database followed by non paged pool [MiVaPfnDatabase/MiVaNonPagedPool]
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#define MI_NONPAGED_POOL_END (PVOID)0xFFFFFFFFFFBFFFFFULL
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//#define MM_HAL_VA_START 0xFFFFFFFFFFC00000ULL // 4 MB HAL mappings, defined in NDK [MiVaHal]
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#define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
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#define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
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/* WOW64 address definitions */
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#define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
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#define MM_SYSTEM_RANGE_START_WOW64 0x80000000
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/* The size of the virtual memory area that is mapped using a single PDE */
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#define PDE_MAPPED_VA (PTE_PER_PAGE * PAGE_SIZE)
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/* Misc address definitions */
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//#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
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//#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
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//#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
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#define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
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#define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
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#define MI_MAPPING_RANGE_START HYPER_SPACE
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#define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
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#define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE)
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#define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE)
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#define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
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/* Memory sizes */
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#define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
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#define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
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#define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
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#define MI_SYSTEM_VIEW_SIZE (104 * _1MB)
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#define MI_SESSION_VIEW_SIZE (104 * _1MB)
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#define MI_SESSION_POOL_SIZE (64 * _1MB)
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#define MI_SESSION_IMAGE_SIZE (16 * _1MB)
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#define MI_SESSION_WORKING_SET_SIZE (16 * _1MB)
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#define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
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MI_SESSION_POOL_SIZE + \
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MI_SESSION_IMAGE_SIZE + \
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MI_SESSION_WORKING_SET_SIZE)
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#define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
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#define MI_ALLOCATION_FRAGMENT (64 * _1KB)
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#define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
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/* Misc constants */
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#define MM_PTE_SOFTWARE_PROTECTION_BITS 5
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#define MI_MIN_SECONDARY_COLORS 8
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#define MI_SECONDARY_COLORS 64
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#define MI_MAX_SECONDARY_COLORS 1024
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#define MI_NUMBER_SYSTEM_PTES 22000
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#define MI_MAX_FREE_PAGE_LISTS 4
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#define MI_HYPERSPACE_PTES (256 - 1)
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#define MI_ZERO_PTES (32)
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#define MI_MAX_ZERO_BITS 53
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#define SESSION_POOL_LOOKASIDES 21
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/* MMPTE related defines */
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#define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
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#define MM_EMPTY_LIST ((ULONG_PTR)-1)
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