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[HALX86] Trailing whitespace fixes only.
This commit is contained in:
Hermès Bélusca-Maïto
parent
03a9ccce65
commit
00cb464d9d
@ -81,35 +81,35 @@ HalpPushInt(IN PHAL_BIOS_FRAME BiosFrame,
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{
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PUSHORT Stack;
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ULONG Eip;
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/* Calculate stack address (SP) */
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Stack = (PUSHORT)(BiosFrame->SsBase + (BiosFrame->Esp & 0xFFFF));
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/* Push EFlags */
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Stack--;
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*Stack = BiosFrame->EFlags & 0xFFFF;
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/* Push CS */
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Stack--;
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*Stack = BiosFrame->SegCs & 0xFFFF;
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/* Push IP */
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Stack--;
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*Stack = BiosFrame->Eip & 0xFFFF;
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/* Compute new CS:IP from the IVT address for this interrupt entry */
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Eip = *(PULONG)(Interrupt * 4);
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BiosFrame->Eip = Eip & 0xFFFF;
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BiosFrame->SegCs = Eip >> 16;
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/* Update stack address */
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BiosFrame->Esp = (ULONG_PTR)Stack & 0xFFFF;
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/* Update CS to linear */
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BiosFrame->CsBase = BiosFrame->SegCs << 4;
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BiosFrame->CsLimit = 0xFFFF;
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BiosFrame->CsFlags = 0;
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/* We're done */
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return TRUE;
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}
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@ -120,19 +120,19 @@ HalpOpcodeINTnn(IN PHAL_BIOS_FRAME BiosFrame)
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{
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UCHAR Interrupt;
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PKTRAP_FRAME TrapFrame;
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/* Convert SS to linear */
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BiosFrame->SsBase = BiosFrame->SegSs << 4;
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BiosFrame->SsLimit = 0xFFFF;
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BiosFrame->SsFlags = 0;
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/* Increase EIP and validate */
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BiosFrame->Eip++;
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if (BiosFrame->Eip > BiosFrame->CsLimit) return FALSE;
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/* Read interrupt number */
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Interrupt = *(PUCHAR)(BiosFrame->CsBase + BiosFrame->Eip);
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/* Increase EIP and push the interrupt */
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BiosFrame->Eip++;
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if (HalpPushInt(BiosFrame, Interrupt))
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@ -143,11 +143,11 @@ HalpOpcodeINTnn(IN PHAL_BIOS_FRAME BiosFrame)
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TrapFrame->HardwareEsp = BiosFrame->Esp;
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TrapFrame->SegCs = BiosFrame->SegCs;
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TrapFrame->EFlags = BiosFrame->EFlags;
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/* Success */
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return TRUE;
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}
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/* Failure */
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return FALSE;
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}
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@ -158,7 +158,7 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
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{
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UCHAR Instruction;
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HAL_BIOS_FRAME BiosFrame;
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/* Fill out the BIOS frame */
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BiosFrame.TrapFrame = TrapFrame;
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BiosFrame.SegSs = TrapFrame->HardwareSegSs;
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@ -167,15 +167,15 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
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BiosFrame.SegCs = TrapFrame->SegCs;
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BiosFrame.Eip = TrapFrame->Eip;
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BiosFrame.Prefix = 0;
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/* Convert CS to linear */
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BiosFrame.CsBase = BiosFrame.SegCs << 4;
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BiosFrame.CsLimit = 0xFFFF;
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BiosFrame.CsFlags = 0;
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/* Validate IP */
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if (BiosFrame.Eip > BiosFrame.CsLimit) return FALSE;
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/* Read IP */
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Instruction = *(PUCHAR)(BiosFrame.CsBase + BiosFrame.Eip);
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if (Instruction != 0xCD)
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@ -184,17 +184,17 @@ HalpDispatchV86Opcode(IN PKTRAP_FRAME TrapFrame)
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HalpOpcodeInvalid(&BiosFrame);
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return FALSE;
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}
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/* Handle the interrupt */
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if (HalpOpcodeINTnn(&BiosFrame))
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{
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/* Update EIP */
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TrapFrame->Eip = BiosFrame.Eip;
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/* We're done */
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return TRUE;
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}
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/* Failure */
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return FALSE;
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}
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@ -209,7 +209,7 @@ HalpTrap0DHandler(IN PKTRAP_FRAME TrapFrame)
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{
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/* Enter the trap */
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KiEnterTrap(TrapFrame);
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/* Check if this is a V86 trap */
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if (TrapFrame->EFlags & EFLAGS_V86_MASK)
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{
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@ -217,7 +217,7 @@ HalpTrap0DHandler(IN PKTRAP_FRAME TrapFrame)
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HalpDispatchV86Opcode(TrapFrame);
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KiEoiHelper(TrapFrame);
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}
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/* Strange, it isn't! This can happen during NMI */
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DPRINT1("HAL: Trap0D while not in V86 mode\n");
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KiDumpTrapFrame(TrapFrame);
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@ -235,7 +235,7 @@ HalpTrap06(VOID)
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Ke386SetDs(KGDT_R3_DATA | RPL_MASK);
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Ke386SetFs(KGDT_R0_PCR);
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/* Restore the stack */
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/* Restore the stack */
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KeGetPcr()->TSS->Esp0 = HalpSavedEsp0;
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/* Return back to where we left */
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@ -252,24 +252,24 @@ HalpBiosCall(VOID)
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/* Must be volatile so it doesn't get optimized away! */
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volatile KTRAP_FRAME V86TrapFrame;
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ULONG_PTR StackOffset, CodeOffset;
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/* Save the context, check for return */
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if (_setjmp(HalpSavedContext))
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{
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/* Returned from v86 */
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return;
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}
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/* Kill alignment faults */
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__writecr0(__readcr0() & ~CR0_AM);
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/* Set new stack address */
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KeGetPcr()->TSS->Esp0 = (ULONG)&V86TrapFrame - 0x20 - sizeof(FX_SAVE_AREA);
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/* Compute segmented IP and SP offsets */
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StackOffset = (ULONG_PTR)&HalpRealModeEnd - 4 - (ULONG_PTR)HalpRealModeStart;
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CodeOffset = (ULONG_PTR)HalpRealModeStart & 0xFFF;
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/* Now build the V86 trap frame */
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V86TrapFrame.V86Es = 0;
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V86TrapFrame.V86Ds = 0;
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@ -280,7 +280,7 @@ HalpBiosCall(VOID)
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V86TrapFrame.EFlags = __readeflags() | EFLAGS_V86_MASK | EFLAGS_IOPL;
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V86TrapFrame.SegCs = 0x2000;
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V86TrapFrame.Eip = CodeOffset;
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/* Exit to V86 mode */
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HalpExitToV86((PKTRAP_FRAME)&V86TrapFrame);
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}
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@ -339,7 +339,7 @@ HalpBorrowTss(VOID)
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TssGdt->HighWord.Bits.Type = I386_TSS;
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TssGdt->HighWord.Bits.Pres = 1;
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TssGdt->HighWord.Bits.Dpl = 0;
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//
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// Load new TSS and return old one
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//
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@ -353,7 +353,7 @@ HalpReturnTss(VOID)
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{
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PKGDTENTRY TssGdt;
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PKTSS TssBase;
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//
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// Get the original TSS
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//
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@ -497,7 +497,7 @@ HalpMapRealModeMemory(VOID)
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// Map the physical address into our real-mode region
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//
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Pte->PageFrameNumber = V86Pte->PageFrameNumber;
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//
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// Keep going until we've reached the end of our region
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//
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@ -557,7 +557,7 @@ HalpSetupRealModeIoPermissionsAndTask(VOID)
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//
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// Save our stack pointer
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//
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HalpSavedEsp0 = KeGetPcr()->TSS->Esp0;
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HalpSavedEsp0 = KeGetPcr()->TSS->Esp0;
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}
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VOID
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@ -661,7 +661,7 @@ HalpBiosDisplayReset(VOID)
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//
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HalpMapRealModeMemory();
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//
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//
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// On P5, the first 7 entries of the IDT are write protected to work around
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// the cmpxchg8b lock errata. Unprotect them here so we can set our custom
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// invalid op-code handler.
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@ -699,7 +699,7 @@ HalpBiosDisplayReset(VOID)
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// Restore TSS and IOPM
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//
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HalpRestoreIoPermissionsAndTask();
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//
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// Restore low memory mapping
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//
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