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ad8a4570ad
The code handling the I/O instructions for KVM decodes the instruction itself. In TCG mode also pass the full instruction word to the helpers. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
597 lines
16 KiB
C
597 lines
16 KiB
C
/*
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* S/390 misc helper routines
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2009 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/memory.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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#include <string.h>
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#include "sysemu/kvm.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#ifdef CONFIG_KVM
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#include <linux/kvm.h>
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#endif
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#include "exec/cpu_ldst.h"
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#include "hw/watchdog/wdt_diag288.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "sysemu/cpus.h"
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#include "sysemu/sysemu.h"
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#include "hw/s390x/ebcdic.h"
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#include "hw/s390x/ipl.h"
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#endif
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/* #define DEBUG_HELPER */
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#ifdef DEBUG_HELPER
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#define HELPER_LOG(x...) qemu_log(x)
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#else
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#define HELPER_LOG(x...)
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#endif
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/* Raise an exception dynamically from a helper function. */
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void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
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uintptr_t retaddr)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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int t;
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cs->exception_index = EXCP_PGM;
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env->int_pgm_code = excp;
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/* Use the (ultimate) callers address to find the insn that trapped. */
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cpu_restore_state(cs, retaddr);
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/* Advance past the insn. */
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t = cpu_ldub_code(env, env->psw.addr);
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env->int_pgm_ilen = t = get_ilen(t);
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env->psw.addr += t;
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cpu_loop_exit(cs);
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}
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/* Raise an exception statically from a TB. */
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void HELPER(exception)(CPUS390XState *env, uint32_t excp)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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HELPER_LOG("%s: exception %d\n", __func__, excp);
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cs->exception_index = excp;
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cpu_loop_exit(cs);
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}
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#ifndef CONFIG_USER_ONLY
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void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
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env->psw.addr);
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if (kvm_enabled()) {
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#ifdef CONFIG_KVM
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struct kvm_s390_irq irq = {
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.type = KVM_S390_PROGRAM_INT,
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.u.pgm.code = code,
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};
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kvm_s390_vcpu_interrupt(cpu, &irq);
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#endif
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} else {
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CPUState *cs = CPU(cpu);
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env->int_pgm_code = code;
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env->int_pgm_ilen = ilen;
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cs->exception_index = EXCP_PGM;
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cpu_loop_exit(cs);
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}
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}
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/* SCLP service call */
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uint32_t HELPER(servc)(CPUS390XState *env, uint64_t r1, uint64_t r2)
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{
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int r = sclp_service_call(env, r1, r2);
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if (r < 0) {
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program_interrupt(env, -r, 4);
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return 0;
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}
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return r;
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}
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#ifndef CONFIG_USER_ONLY
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static int modified_clear_reset(S390CPU *cpu)
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{
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUState *t;
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pause_all_vcpus();
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cpu_synchronize_all_states();
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CPU_FOREACH(t) {
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run_on_cpu(t, s390_do_cpu_full_reset, t);
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}
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cmma_reset(cpu);
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io_subsystem_reset();
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scc->load_normal(CPU(cpu));
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cpu_synchronize_all_post_reset();
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resume_all_vcpus();
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return 0;
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}
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static int load_normal_reset(S390CPU *cpu)
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{
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUState *t;
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pause_all_vcpus();
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cpu_synchronize_all_states();
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CPU_FOREACH(t) {
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run_on_cpu(t, s390_do_cpu_reset, t);
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}
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cmma_reset(cpu);
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io_subsystem_reset();
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scc->initial_cpu_reset(CPU(cpu));
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scc->load_normal(CPU(cpu));
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cpu_synchronize_all_post_reset();
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resume_all_vcpus();
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return 0;
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}
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int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3)
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{
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uint64_t func = env->regs[r1];
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uint64_t timeout = env->regs[r1 + 1];
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uint64_t action = env->regs[r3];
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Object *obj;
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DIAG288State *diag288;
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DIAG288Class *diag288_class;
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if (r1 % 2 || action != 0) {
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return -1;
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}
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/* Timeout must be more than 15 seconds except for timer deletion */
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if (func != WDT_DIAG288_CANCEL && timeout < 15) {
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return -1;
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}
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obj = object_resolve_path_type("", TYPE_WDT_DIAG288, NULL);
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if (!obj) {
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return -1;
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}
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diag288 = DIAG288(obj);
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diag288_class = DIAG288_GET_CLASS(diag288);
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return diag288_class->handle_timer(diag288, func, timeout);
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}
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#define DIAG_308_RC_OK 0x0001
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#define DIAG_308_RC_NO_CONF 0x0102
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#define DIAG_308_RC_INVALID 0x0402
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void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3)
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{
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uint64_t addr = env->regs[r1];
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uint64_t subcode = env->regs[r3];
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IplParameterBlock *iplb;
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if (env->psw.mask & PSW_MASK_PSTATE) {
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program_interrupt(env, PGM_PRIVILEGED, ILEN_LATER_INC);
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return;
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}
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if ((subcode & ~0x0ffffULL) || (subcode > 6)) {
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program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
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return;
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}
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switch (subcode) {
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case 0:
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modified_clear_reset(s390_env_get_cpu(env));
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if (tcg_enabled()) {
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cpu_loop_exit(CPU(s390_env_get_cpu(env)));
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}
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break;
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case 1:
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load_normal_reset(s390_env_get_cpu(env));
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if (tcg_enabled()) {
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cpu_loop_exit(CPU(s390_env_get_cpu(env)));
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}
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break;
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case 3:
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s390_reipl_request();
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if (tcg_enabled()) {
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cpu_loop_exit(CPU(s390_env_get_cpu(env)));
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}
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break;
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case 5:
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if ((r1 & 1) || (addr & 0x0fffULL)) {
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program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
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return;
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}
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if (!address_space_access_valid(&address_space_memory, addr,
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sizeof(IplParameterBlock), false)) {
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program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC);
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return;
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}
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iplb = g_malloc0(sizeof(struct IplParameterBlock));
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cpu_physical_memory_read(addr, iplb, sizeof(struct IplParameterBlock));
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if (!s390_ipl_update_diag308(iplb)) {
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env->regs[r1 + 1] = DIAG_308_RC_OK;
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} else {
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env->regs[r1 + 1] = DIAG_308_RC_INVALID;
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}
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g_free(iplb);
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return;
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case 6:
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if ((r1 & 1) || (addr & 0x0fffULL)) {
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program_interrupt(env, PGM_SPECIFICATION, ILEN_LATER_INC);
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return;
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}
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if (!address_space_access_valid(&address_space_memory, addr,
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sizeof(IplParameterBlock), true)) {
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program_interrupt(env, PGM_ADDRESSING, ILEN_LATER_INC);
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return;
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}
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iplb = s390_ipl_get_iplb();
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if (iplb) {
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cpu_physical_memory_write(addr, iplb,
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sizeof(struct IplParameterBlock));
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env->regs[r1 + 1] = DIAG_308_RC_OK;
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} else {
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env->regs[r1 + 1] = DIAG_308_RC_NO_CONF;
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}
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return;
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default:
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hw_error("Unhandled diag308 subcode %" PRIx64, subcode);
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break;
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}
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}
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#endif
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void HELPER(diag)(CPUS390XState *env, uint32_t r1, uint32_t r3, uint32_t num)
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{
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uint64_t r;
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switch (num) {
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case 0x500:
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/* KVM hypercall */
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r = s390_virtio_hypercall(env);
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break;
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case 0x44:
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/* yield */
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r = 0;
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break;
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case 0x308:
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/* ipl */
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handle_diag_308(env, r1, r3);
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r = 0;
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break;
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default:
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r = -1;
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break;
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}
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if (r) {
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program_interrupt(env, PGM_OPERATION, ILEN_LATER_INC);
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}
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}
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/* Set Prefix */
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void HELPER(spx)(CPUS390XState *env, uint64_t a1)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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uint32_t prefix = a1 & 0x7fffe000;
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env->psa = prefix;
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qemu_log("prefix: %#x\n", prefix);
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tlb_flush_page(cs, 0);
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tlb_flush_page(cs, TARGET_PAGE_SIZE);
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}
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/* Store Clock */
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uint64_t HELPER(stck)(CPUS390XState *env)
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{
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uint64_t time;
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time = env->tod_offset +
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time2tod(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - env->tod_basetime);
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return time;
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}
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/* Set Clock Comparator */
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void HELPER(sckc)(CPUS390XState *env, uint64_t time)
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{
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if (time == -1ULL) {
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return;
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}
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env->ckc = time;
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/* difference between origins */
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time -= env->tod_offset;
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/* nanoseconds */
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time = tod2time(time);
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timer_mod(env->tod_timer, env->tod_basetime + time);
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}
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/* Store Clock Comparator */
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uint64_t HELPER(stckc)(CPUS390XState *env)
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{
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return env->ckc;
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}
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/* Set CPU Timer */
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void HELPER(spt)(CPUS390XState *env, uint64_t time)
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{
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if (time == -1ULL) {
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return;
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}
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/* nanoseconds */
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time = tod2time(time);
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env->cputm = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + time;
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timer_mod(env->cpu_timer, env->cputm);
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}
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/* Store CPU Timer */
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uint64_t HELPER(stpt)(CPUS390XState *env)
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{
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return time2tod(env->cputm - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
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}
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/* Store System Information */
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uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0,
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uint64_t r0, uint64_t r1)
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{
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int cc = 0;
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int sel1, sel2;
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if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
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((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
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/* valid function code, invalid reserved bits */
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program_interrupt(env, PGM_SPECIFICATION, 2);
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}
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sel1 = r0 & STSI_R0_SEL1_MASK;
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sel2 = r1 & STSI_R1_SEL2_MASK;
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/* XXX: spec exception if sysib is not 4k-aligned */
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switch (r0 & STSI_LEVEL_MASK) {
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case STSI_LEVEL_1:
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if ((sel1 == 1) && (sel2 == 1)) {
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/* Basic Machine Configuration */
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struct sysib_111 sysib;
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memset(&sysib, 0, sizeof(sysib));
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ebcdic_put(sysib.manuf, "QEMU ", 16);
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/* same as machine type number in STORE CPU ID */
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ebcdic_put(sysib.type, "QEMU", 4);
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/* same as model number in STORE CPU ID */
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ebcdic_put(sysib.model, "QEMU ", 16);
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ebcdic_put(sysib.sequence, "QEMU ", 16);
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ebcdic_put(sysib.plant, "QEMU", 4);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else if ((sel1 == 2) && (sel2 == 1)) {
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/* Basic Machine CPU */
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struct sysib_121 sysib;
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memset(&sysib, 0, sizeof(sysib));
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/* XXX make different for different CPUs? */
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ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
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ebcdic_put(sysib.plant, "QEMU", 4);
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stw_p(&sysib.cpu_addr, env->cpu_num);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else if ((sel1 == 2) && (sel2 == 2)) {
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/* Basic Machine CPUs */
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struct sysib_122 sysib;
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memset(&sysib, 0, sizeof(sysib));
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stl_p(&sysib.capability, 0x443afc29);
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/* XXX change when SMP comes */
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stw_p(&sysib.total_cpus, 1);
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stw_p(&sysib.active_cpus, 1);
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stw_p(&sysib.standby_cpus, 0);
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stw_p(&sysib.reserved_cpus, 0);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else {
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cc = 3;
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}
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break;
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case STSI_LEVEL_2:
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{
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if ((sel1 == 2) && (sel2 == 1)) {
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/* LPAR CPU */
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struct sysib_221 sysib;
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memset(&sysib, 0, sizeof(sysib));
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/* XXX make different for different CPUs? */
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ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
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ebcdic_put(sysib.plant, "QEMU", 4);
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stw_p(&sysib.cpu_addr, env->cpu_num);
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stw_p(&sysib.cpu_id, 0);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else if ((sel1 == 2) && (sel2 == 2)) {
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/* LPAR CPUs */
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struct sysib_222 sysib;
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memset(&sysib, 0, sizeof(sysib));
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stw_p(&sysib.lpar_num, 0);
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sysib.lcpuc = 0;
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/* XXX change when SMP comes */
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stw_p(&sysib.total_cpus, 1);
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stw_p(&sysib.conf_cpus, 1);
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stw_p(&sysib.standby_cpus, 0);
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stw_p(&sysib.reserved_cpus, 0);
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ebcdic_put(sysib.name, "QEMU ", 8);
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stl_p(&sysib.caf, 1000);
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stw_p(&sysib.dedicated_cpus, 0);
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stw_p(&sysib.shared_cpus, 0);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else {
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cc = 3;
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}
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break;
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}
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case STSI_LEVEL_3:
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{
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if ((sel1 == 2) && (sel2 == 2)) {
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/* VM CPUs */
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struct sysib_322 sysib;
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memset(&sysib, 0, sizeof(sysib));
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sysib.count = 1;
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/* XXX change when SMP comes */
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stw_p(&sysib.vm[0].total_cpus, 1);
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stw_p(&sysib.vm[0].conf_cpus, 1);
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stw_p(&sysib.vm[0].standby_cpus, 0);
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stw_p(&sysib.vm[0].reserved_cpus, 0);
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ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
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stl_p(&sysib.vm[0].caf, 1000);
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ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
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cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
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} else {
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cc = 3;
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}
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break;
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}
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case STSI_LEVEL_CURRENT:
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env->regs[0] = STSI_LEVEL_3;
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break;
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default:
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cc = 3;
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break;
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}
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return cc;
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}
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uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
|
|
uint64_t cpu_addr)
|
|
{
|
|
int cc = SIGP_CC_ORDER_CODE_ACCEPTED;
|
|
|
|
HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
|
|
__func__, order_code, r1, cpu_addr);
|
|
|
|
/* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
|
|
as parameter (input). Status (output) is always R1. */
|
|
|
|
switch (order_code) {
|
|
case SIGP_SET_ARCH:
|
|
/* switch arch */
|
|
break;
|
|
case SIGP_SENSE:
|
|
/* enumerate CPU status */
|
|
if (cpu_addr) {
|
|
/* XXX implement when SMP comes */
|
|
return 3;
|
|
}
|
|
env->regs[r1] &= 0xffffffff00000000ULL;
|
|
cc = 1;
|
|
break;
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
case SIGP_RESTART:
|
|
qemu_system_reset_request();
|
|
cpu_loop_exit(CPU(s390_env_get_cpu(env)));
|
|
break;
|
|
case SIGP_STOP:
|
|
qemu_system_shutdown_request();
|
|
cpu_loop_exit(CPU(s390_env_get_cpu(env)));
|
|
break;
|
|
#endif
|
|
default:
|
|
/* unknown sigp */
|
|
fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
|
|
cc = SIGP_CC_NOT_OPERATIONAL;
|
|
}
|
|
|
|
return cc;
|
|
}
|
|
#endif
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
void HELPER(xsch)(CPUS390XState *env, uint64_t r1)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_xsch(cpu, r1);
|
|
}
|
|
|
|
void HELPER(csch)(CPUS390XState *env, uint64_t r1)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_csch(cpu, r1);
|
|
}
|
|
|
|
void HELPER(hsch)(CPUS390XState *env, uint64_t r1)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_hsch(cpu, r1);
|
|
}
|
|
|
|
void HELPER(msch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_msch(cpu, r1, inst >> 16);
|
|
}
|
|
|
|
void HELPER(rchp)(CPUS390XState *env, uint64_t r1)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_rchp(cpu, r1);
|
|
}
|
|
|
|
void HELPER(rsch)(CPUS390XState *env, uint64_t r1)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_rsch(cpu, r1);
|
|
}
|
|
|
|
void HELPER(ssch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_ssch(cpu, r1, inst >> 16);
|
|
}
|
|
|
|
void HELPER(stsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_stsch(cpu, r1, inst >> 16);
|
|
}
|
|
|
|
void HELPER(tsch)(CPUS390XState *env, uint64_t r1, uint64_t inst)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_tsch(cpu, r1, inst >> 16);
|
|
}
|
|
|
|
void HELPER(chsc)(CPUS390XState *env, uint64_t inst)
|
|
{
|
|
S390CPU *cpu = s390_env_get_cpu(env);
|
|
ioinst_handle_chsc(cpu, inst >> 16);
|
|
}
|
|
#endif
|