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c255ac6012
s390_cpu_handle_mmu_fault currently looks at the current ASC mode defined in PSW mask instead of the MMU index. This prevent emulating easily instructions using a specific ASC mode. Fix that by using the MMU index converted back to ASC using the just added cpu_mmu_idx_to_asc function. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
561 lines
15 KiB
C
561 lines
15 KiB
C
/*
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* S/390 helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu/timer.h"
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#include "exec/cpu_ldst.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/sysemu.h"
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#endif
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//#define DEBUG_S390
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//#define DEBUG_S390_STDOUT
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#ifdef DEBUG_S390
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#ifdef DEBUG_S390_STDOUT
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#define DPRINTF(fmt, ...) \
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do { fprintf(stderr, fmt, ## __VA_ARGS__); \
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qemu_log(fmt, ##__VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) \
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do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
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#endif
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#else
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#define DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#ifndef CONFIG_USER_ONLY
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void s390x_tod_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_TOD;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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void s390x_cpu_timer(void *opaque)
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{
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S390CPU *cpu = opaque;
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CPUS390XState *env = &cpu->env;
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env->pending_int |= INTERRUPT_CPUTIMER;
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cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
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}
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#endif
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S390CPU *cpu_s390x_init(const char *cpu_model)
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{
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S390CPU *cpu;
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cpu = S390_CPU(object_new(TYPE_S390_CPU));
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object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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return cpu;
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}
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#if defined(CONFIG_USER_ONLY)
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void s390_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = -1;
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}
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int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
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int rw, int mmu_idx)
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{
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S390CPU *cpu = S390_CPU(cs);
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cs->exception_index = EXCP_PGM;
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cpu->env.int_pgm_code = PGM_ADDRESSING;
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/* On real machines this value is dropped into LowMem. Since this
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is userland, simply put this someplace that cpu_loop can find it. */
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cpu->env.__excp_addr = address;
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return 1;
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}
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#else /* !CONFIG_USER_ONLY */
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/* Ensure to exit the TB after this call! */
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void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen)
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{
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CPUState *cs = CPU(s390_env_get_cpu(env));
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cs->exception_index = EXCP_PGM;
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env->int_pgm_code = code;
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env->int_pgm_ilen = ilen;
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}
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int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
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int rw, int mmu_idx)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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uint64_t asc = cpu_mmu_idx_to_asc(mmu_idx);
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target_ulong vaddr, raddr;
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int prot;
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DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, orig_vaddr, rw, mmu_idx);
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orig_vaddr &= TARGET_PAGE_MASK;
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vaddr = orig_vaddr;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot, true)) {
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/* Translation ended in exception */
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return 1;
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}
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/* check out of RAM access */
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if (raddr > (ram_size + virtio_size)) {
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DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
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(uint64_t)raddr, (uint64_t)ram_size);
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trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
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return 1;
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}
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qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
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__func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
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tlb_set_page(cs, orig_vaddr, raddr, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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{
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S390CPU *cpu = S390_CPU(cs);
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CPUS390XState *env = &cpu->env;
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target_ulong raddr;
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int prot;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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}
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mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false);
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return raddr;
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}
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hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr)
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{
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hwaddr phys_addr;
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target_ulong page;
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page = vaddr & TARGET_PAGE_MASK;
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phys_addr = cpu_get_phys_page_debug(cs, page);
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phys_addr += (vaddr & ~TARGET_PAGE_MASK);
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return phys_addr;
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}
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void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
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{
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env->psw.addr = addr;
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env->psw.mask = mask;
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if (tcg_enabled()) {
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env->cc_op = (mask >> 44) & 3;
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}
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if (mask & PSW_MASK_WAIT) {
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S390CPU *cpu = s390_env_get_cpu(env);
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if (s390_cpu_halt(cpu) == 0) {
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#ifndef CONFIG_USER_ONLY
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qemu_system_shutdown_request();
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#endif
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}
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}
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}
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static uint64_t get_psw_mask(CPUS390XState *env)
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{
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uint64_t r = env->psw.mask;
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if (tcg_enabled()) {
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env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst,
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env->cc_vr);
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r &= ~PSW_MASK_CC;
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assert(!(env->cc_op & ~3));
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r |= (uint64_t)env->cc_op << 44;
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}
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return r;
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}
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static LowCore *cpu_map_lowcore(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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LowCore *lowcore;
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hwaddr len = sizeof(LowCore);
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lowcore = cpu_physical_memory_map(env->psa, &len, 1);
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if (len < sizeof(LowCore)) {
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cpu_abort(CPU(cpu), "Could not map lowcore\n");
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}
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return lowcore;
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}
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static void cpu_unmap_lowcore(LowCore *lowcore)
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{
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cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
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}
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void do_restart_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->restart_new_psw.mask);
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addr = be64_to_cpu(lowcore->restart_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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}
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static void do_svc_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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lowcore = cpu_map_lowcore(env);
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lowcore->svc_code = cpu_to_be16(env->int_svc_code);
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lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
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lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
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mask = be64_to_cpu(lowcore->svc_new_psw.mask);
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addr = be64_to_cpu(lowcore->svc_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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load_psw(env, mask, addr);
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}
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static void do_program_interrupt(CPUS390XState *env)
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{
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uint64_t mask, addr;
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LowCore *lowcore;
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int ilen = env->int_pgm_ilen;
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switch (ilen) {
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case ILEN_LATER:
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ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
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break;
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case ILEN_LATER_INC:
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ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
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env->psw.addr += ilen;
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break;
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default:
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assert(ilen == 2 || ilen == 4 || ilen == 6);
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}
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qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
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__func__, env->int_pgm_code, ilen);
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lowcore = cpu_map_lowcore(env);
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lowcore->pgm_ilen = cpu_to_be16(ilen);
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lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
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lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->program_new_psw.mask);
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addr = be64_to_cpu(lowcore->program_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
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env->int_pgm_code, ilen, env->psw.mask,
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env->psw.addr);
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load_psw(env, mask, addr);
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}
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#define VIRTIO_SUBCODE_64 0x0D00
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static void do_ext_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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uint64_t mask, addr;
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LowCore *lowcore;
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ExtQueue *q;
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if (!(env->psw.mask & PSW_MASK_EXT)) {
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cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
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}
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if (env->ext_index < 0 || env->ext_index >= MAX_EXT_QUEUE) {
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cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
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}
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q = &env->ext_queue[env->ext_index];
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lowcore = cpu_map_lowcore(env);
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lowcore->ext_int_code = cpu_to_be16(q->code);
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lowcore->ext_params = cpu_to_be32(q->param);
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lowcore->ext_params2 = cpu_to_be64(q->param64);
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lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
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lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
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mask = be64_to_cpu(lowcore->external_new_psw.mask);
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addr = be64_to_cpu(lowcore->external_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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env->ext_index--;
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if (env->ext_index == -1) {
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env->pending_int &= ~INTERRUPT_EXT;
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}
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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load_psw(env, mask, addr);
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}
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static void do_io_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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LowCore *lowcore;
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IOIntQueue *q;
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uint8_t isc;
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int disable = 1;
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int found = 0;
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if (!(env->psw.mask & PSW_MASK_IO)) {
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cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
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}
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for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
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uint64_t isc_bits;
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if (env->io_index[isc] < 0) {
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continue;
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}
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if (env->io_index[isc] >= MAX_IO_QUEUE) {
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cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
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isc, env->io_index[isc]);
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}
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q = &env->io_queue[env->io_index[isc]][isc];
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isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
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if (!(env->cregs[6] & isc_bits)) {
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disable = 0;
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continue;
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}
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if (!found) {
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uint64_t mask, addr;
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found = 1;
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lowcore = cpu_map_lowcore(env);
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lowcore->subchannel_id = cpu_to_be16(q->id);
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lowcore->subchannel_nr = cpu_to_be16(q->nr);
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lowcore->io_int_parm = cpu_to_be32(q->parm);
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lowcore->io_int_word = cpu_to_be32(q->word);
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lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
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mask = be64_to_cpu(lowcore->io_new_psw.mask);
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addr = be64_to_cpu(lowcore->io_new_psw.addr);
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cpu_unmap_lowcore(lowcore);
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env->io_index[isc]--;
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DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
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env->psw.mask, env->psw.addr);
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load_psw(env, mask, addr);
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}
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if (env->io_index[isc] >= 0) {
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disable = 0;
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}
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continue;
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}
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if (disable) {
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env->pending_int &= ~INTERRUPT_IO;
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}
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}
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static void do_mchk_interrupt(CPUS390XState *env)
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{
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S390CPU *cpu = s390_env_get_cpu(env);
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uint64_t mask, addr;
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LowCore *lowcore;
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MchkQueue *q;
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int i;
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if (!(env->psw.mask & PSW_MASK_MCHECK)) {
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cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
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}
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if (env->mchk_index < 0 || env->mchk_index >= MAX_MCHK_QUEUE) {
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cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
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}
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q = &env->mchk_queue[env->mchk_index];
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if (q->type != 1) {
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/* Don't know how to handle this... */
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cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
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}
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if (!(env->cregs[14] & (1 << 28))) {
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/* CRW machine checks disabled */
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return;
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}
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lowcore = cpu_map_lowcore(env);
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for (i = 0; i < 16; i++) {
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lowcore->floating_pt_save_area[i] = cpu_to_be64(get_freg(env, i)->ll);
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lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
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lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
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lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
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}
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lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
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lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
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lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
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lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
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lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
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lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
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lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
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lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
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lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
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lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
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lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
|
|
mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
|
|
addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
|
|
|
|
cpu_unmap_lowcore(lowcore);
|
|
|
|
env->mchk_index--;
|
|
if (env->mchk_index == -1) {
|
|
env->pending_int &= ~INTERRUPT_MCHK;
|
|
}
|
|
|
|
DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
|
|
env->psw.mask, env->psw.addr);
|
|
|
|
load_psw(env, mask, addr);
|
|
}
|
|
|
|
void s390_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
|
|
__func__, cs->exception_index, env->psw.addr);
|
|
|
|
s390_cpu_set_state(CPU_STATE_OPERATING, cpu);
|
|
/* handle machine checks */
|
|
if ((env->psw.mask & PSW_MASK_MCHECK) &&
|
|
(cs->exception_index == -1)) {
|
|
if (env->pending_int & INTERRUPT_MCHK) {
|
|
cs->exception_index = EXCP_MCHK;
|
|
}
|
|
}
|
|
/* handle external interrupts */
|
|
if ((env->psw.mask & PSW_MASK_EXT) &&
|
|
cs->exception_index == -1) {
|
|
if (env->pending_int & INTERRUPT_EXT) {
|
|
/* code is already in env */
|
|
cs->exception_index = EXCP_EXT;
|
|
} else if (env->pending_int & INTERRUPT_TOD) {
|
|
cpu_inject_ext(cpu, 0x1004, 0, 0);
|
|
cs->exception_index = EXCP_EXT;
|
|
env->pending_int &= ~INTERRUPT_EXT;
|
|
env->pending_int &= ~INTERRUPT_TOD;
|
|
} else if (env->pending_int & INTERRUPT_CPUTIMER) {
|
|
cpu_inject_ext(cpu, 0x1005, 0, 0);
|
|
cs->exception_index = EXCP_EXT;
|
|
env->pending_int &= ~INTERRUPT_EXT;
|
|
env->pending_int &= ~INTERRUPT_TOD;
|
|
}
|
|
}
|
|
/* handle I/O interrupts */
|
|
if ((env->psw.mask & PSW_MASK_IO) &&
|
|
(cs->exception_index == -1)) {
|
|
if (env->pending_int & INTERRUPT_IO) {
|
|
cs->exception_index = EXCP_IO;
|
|
}
|
|
}
|
|
|
|
switch (cs->exception_index) {
|
|
case EXCP_PGM:
|
|
do_program_interrupt(env);
|
|
break;
|
|
case EXCP_SVC:
|
|
do_svc_interrupt(env);
|
|
break;
|
|
case EXCP_EXT:
|
|
do_ext_interrupt(env);
|
|
break;
|
|
case EXCP_IO:
|
|
do_io_interrupt(env);
|
|
break;
|
|
case EXCP_MCHK:
|
|
do_mchk_interrupt(env);
|
|
break;
|
|
}
|
|
cs->exception_index = -1;
|
|
|
|
if (!env->pending_int) {
|
|
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
}
|
|
|
|
bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
S390CPU *cpu = S390_CPU(cs);
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
if (env->psw.mask & PSW_MASK_EXT) {
|
|
s390_cpu_do_interrupt(cs);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
#endif /* CONFIG_USER_ONLY */
|