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6b2b2a703c
The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190925143248.10000-12-clg@kaod.org [clg: - reworked model integration into new object class ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
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* ASPEED Watchdog Controller
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*
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* Copyright (C) 2016-2017 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef WDT_ASPEED_H
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#define WDT_ASPEED_H
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#include "hw/misc/aspeed_scu.h"
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_WDT "aspeed.wdt"
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#define ASPEED_WDT(obj) \
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OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
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#define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400"
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#define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500"
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#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600"
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#define ASPEED_WDT_REGS_MAX (0x20 / 4)
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typedef struct AspeedWDTState {
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/*< private >*/
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SysBusDevice parent_obj;
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QEMUTimer *timer;
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/*< public >*/
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MemoryRegion iomem;
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uint32_t regs[ASPEED_WDT_REGS_MAX];
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AspeedSCUState *scu;
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uint32_t pclk_freq;
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} AspeedWDTState;
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#define ASPEED_WDT_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedWDTClass, (klass), TYPE_ASPEED_WDT)
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#define ASPEED_WDT_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedWDTClass, (obj), TYPE_ASPEED_WDT)
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typedef struct AspeedWDTClass {
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SysBusDeviceClass parent_class;
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uint32_t offset;
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uint32_t ext_pulse_width_mask;
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uint32_t reset_ctrl_reg;
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void (*reset_pulse)(AspeedWDTState *s, uint32_t property);
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} AspeedWDTClass;
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#endif /* WDT_ASPEED_H */
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