Michael Clark ef9e41df68 RISC-V: Fix CLINT timecmp low 32-bit writes ... A missing shift made updates to the low order bits of timecmp erroneously copy the old low order bits into the high order bits of the 64-bit timecmp register. Add the missing shift and rename timecmp local variables to timecmp_hi and timecmp_lo. This bug didn't show up as the low order bits are usually written first followed by the high order bits meaning the high order bits contained an invalid value between the timecmp_lo and timecmp_hi update. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Co-Authored-by: Johannes Haring <johannes.haring@gmx.net> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-12-20 12:08:43 -08:00
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Makefile.objs	RISC-V Build Infrastructure	2018-03-07 08:30:28 +13:00
riscv_hart.c	riscv_hart: Fix crash when introspecting the device	2018-07-19 09:05:48 -07:00
riscv_htif.c	hw: Do not include "exec/address-spaces.h" if it is not necessary	2018-06-01 14:15:10 +02:00
sifive_clint.c	RISC-V: Fix CLINT timecmp low 32-bit writes	2018-12-20 12:08:43 -08:00
sifive_e.c	Drop "qemu:" prefix from error_report() arguments	2018-09-24 17:13:07 +02:00
sifive_plic.c	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
sifive_prci.c	SiFive RISC-V PRCI Block	2018-03-07 08:30:28 +13:00
sifive_test.c	SiFive RISC-V Test Finisher	2018-03-07 08:30:28 +13:00
sifive_u.c	sifive_u: Set 'clock-frequency' DT property for SiFive UART	2018-12-20 12:03:26 -08:00
sifive_uart.c	SiFive RISC-V UART Device	2018-03-07 08:30:28 +13:00
spike.c	riscv: spike: Fix memory leak in the board init	2018-11-08 08:41:06 -08:00
virt.c	hw/riscv/virt: Connect the gpex PCIe	2018-12-20 11:45:20 -08:00