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ebe16b9039
These are WARL fields - zero out the bits for unavailable counters and special case the TM bit in mcountinhibit which is hardwired to zero. This patch achieves this by modifying the value written so that any use of the field will see the correctly masked bits. Tested by modifying OpenSBI to write max value to these CSRs and upon subsequent read the appropriate number of bits for number of PMUs is enabled and the TM bit is zero in mcountinhibit. Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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