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38688fdbe9
Currently we have a RXCPU typedef and a RXCPU type checking macro, but OBJECT_DECLARE* would transform the RXCPU macro into a function, and the function name would conflict with the typedef name. Rename the RXCPU* QOM type check macros to RX_CPU*, so we will avoid the conflict and make the macro names consistent with the TYPE_RX_CPU constant name. This will make future conversion to OBJECT_DECLARE* easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20200825192110.3528606-53-ehabkost@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
150 lines
4.5 KiB
C
150 lines
4.5 KiB
C
/*
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* RX emulation
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*
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* Copyright (c) 2019 Yoshinori Sato
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "cpu.h"
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#include "exec/log.h"
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#include "exec/cpu_ldst.h"
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#include "sysemu/sysemu.h"
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#include "hw/irq.h"
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void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte)
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{
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if (env->psw_pm == 0) {
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env->psw_ipl = FIELD_EX32(psw, PSW, IPL);
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if (rte) {
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/* PSW.PM can write RTE and RTFI */
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env->psw_pm = FIELD_EX32(psw, PSW, PM);
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}
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env->psw_u = FIELD_EX32(psw, PSW, U);
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env->psw_i = FIELD_EX32(psw, PSW, I);
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}
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env->psw_o = FIELD_EX32(psw, PSW, O) << 31;
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env->psw_s = FIELD_EX32(psw, PSW, S) << 31;
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env->psw_z = 1 - FIELD_EX32(psw, PSW, Z);
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env->psw_c = FIELD_EX32(psw, PSW, C);
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}
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#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR)
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void rx_cpu_do_interrupt(CPUState *cs)
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{
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RXCPU *cpu = RX_CPU(cs);
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CPURXState *env = &cpu->env;
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int do_irq = cs->interrupt_request & INT_FLAGS;
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uint32_t save_psw;
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env->in_sleep = 0;
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if (env->psw_u) {
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env->usp = env->regs[0];
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} else {
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env->isp = env->regs[0];
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}
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save_psw = rx_cpu_pack_psw(env);
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env->psw_pm = env->psw_i = env->psw_u = 0;
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if (do_irq) {
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if (do_irq & CPU_INTERRUPT_FIR) {
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env->bpc = env->pc;
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env->bpsw = save_psw;
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env->pc = env->fintv;
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env->psw_ipl = 15;
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cs->interrupt_request &= ~CPU_INTERRUPT_FIR;
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qemu_set_irq(env->ack, env->ack_irq);
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qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n");
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} else if (do_irq & CPU_INTERRUPT_HARD) {
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env->isp -= 4;
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cpu_stl_data(env, env->isp, save_psw);
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env->isp -= 4;
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cpu_stl_data(env, env->isp, env->pc);
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env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4);
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env->psw_ipl = env->ack_ipl;
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cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
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qemu_set_irq(env->ack, env->ack_irq);
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qemu_log_mask(CPU_LOG_INT,
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"interrupt 0x%02x raised\n", env->ack_irq);
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}
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} else {
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uint32_t vec = cs->exception_index;
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const char *expname = "unknown exception";
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env->isp -= 4;
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cpu_stl_data(env, env->isp, save_psw);
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env->isp -= 4;
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cpu_stl_data(env, env->isp, env->pc);
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if (vec < 0x100) {
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env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
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} else {
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env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
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}
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switch (vec) {
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case 20:
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expname = "privilege violation";
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break;
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case 21:
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expname = "access exception";
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break;
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case 23:
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expname = "illegal instruction";
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break;
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case 25:
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expname = "fpu exception";
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break;
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case 30:
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expname = "non-maskable interrupt";
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break;
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case 0x100 ... 0x1ff:
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expname = "unconditional trap";
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}
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qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n",
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(vec & 0xff), expname);
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}
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env->regs[0] = env->isp;
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}
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bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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RXCPU *cpu = RX_CPU(cs);
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CPURXState *env = &cpu->env;
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int accept = 0;
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/* hardware interrupt (Normal) */
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if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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env->psw_i && (env->psw_ipl < env->req_ipl)) {
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env->ack_irq = env->req_irq;
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env->ack_ipl = env->req_ipl;
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accept = 1;
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}
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/* hardware interrupt (FIR) */
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if ((interrupt_request & CPU_INTERRUPT_FIR) &&
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env->psw_i && (env->psw_ipl < 15)) {
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accept = 1;
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}
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if (accept) {
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rx_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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return addr;
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}
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