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0722d05ad8
The OCC is an on-chip microcontroller based on a ppc405 core used
for various power management tasks. It comes with a pile of additional
hardware sitting on the PIB (aka XSCOM bus). At this point we don't
emulate it (nor plan to do so). However there is one facility which
is provided by the surrounding hardware that we do need, which is the
interrupt generation facility. OPAL uses it to send itself interrupts
under some circumstances and there are other uses around the corner.
So this implement just enough to support this.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- changed the XSCOM interface to fit new model
- QOMified the model ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
137 lines
3.6 KiB
C
137 lines
3.6 KiB
C
/*
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* QEMU PowerPC PowerNV Emulation of a few OCC related registers
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*
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* Copyright (c) 2015-2017, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "sysemu/sysemu.h"
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#include "target/ppc/cpu.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_xscom.h"
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#include "hw/ppc/pnv_occ.h"
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#define OCB_OCI_OCCMISC 0x4020
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#define OCB_OCI_OCCMISC_AND 0x4021
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#define OCB_OCI_OCCMISC_OR 0x4022
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static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
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{
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bool irq_state;
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val &= 0xffff000000000000ull;
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occ->occmisc = val;
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irq_state = !!(val >> 63);
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pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state);
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}
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static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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uint64_t val = 0;
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switch (offset) {
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case OCB_OCI_OCCMISC:
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val = occ->occmisc;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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return val;
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}
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static void pnv_occ_xscom_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PnvOCC *occ = PNV_OCC(opaque);
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uint32_t offset = addr >> 3;
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switch (offset) {
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case OCB_OCI_OCCMISC_AND:
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pnv_occ_set_misc(occ, occ->occmisc & val);
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break;
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case OCB_OCI_OCCMISC_OR:
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pnv_occ_set_misc(occ, occ->occmisc | val);
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break;
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case OCB_OCI_OCCMISC:
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pnv_occ_set_misc(occ, val);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr);
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}
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}
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static const MemoryRegionOps pnv_occ_xscom_ops = {
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.read = pnv_occ_xscom_read,
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.write = pnv_occ_xscom_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_occ_realize(DeviceState *dev, Error **errp)
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{
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PnvOCC *occ = PNV_OCC(dev);
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Object *obj;
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Error *error = NULL;
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occ->occmisc = 0;
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/* get PSI object from chip */
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obj = object_property_get_link(OBJECT(dev), "psi", &error);
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if (!obj) {
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error_setg(errp, "%s: required link 'psi' not found: %s",
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__func__, error_get_pretty(error));
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return;
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}
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occ->psi = PNV_PSI(obj);
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/* XScom region for OCC registers */
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pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_ops,
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occ, "xscom-occ", PNV_XSCOM_OCC_SIZE);
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}
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static void pnv_occ_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = pnv_occ_realize;
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}
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static const TypeInfo pnv_occ_type_info = {
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.name = TYPE_PNV_OCC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(PnvOCC),
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.class_init = pnv_occ_class_init,
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};
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static void pnv_occ_register_types(void)
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{
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type_register_static(&pnv_occ_type_info);
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}
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type_init(pnv_occ_register_types)
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