aurel32 f364515c83 target-mips: fix FPU in 64-bit mode ... TCG does not allow the same memory location to be aliased in two different global registers, fpu_fpr32 and fpu_fpr64. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6915 c046a42c-6fe2-441c-8c8c-71466251a162		2009-03-28 22:22:50 +00:00
..
cpu.h	target-mips: rename helpers from do_ to helper_	2009-03-08 00:06:01 +00:00
exec.h	target-mips: rename helpers from do_ to helper_	2009-03-08 00:06:01 +00:00
helper.c	Convert references to logfile/loglevel to use qemu_log*() macros	2009-01-15 22:34:14 +00:00
helper.h	target-mips: rename helpers from do_ to helper_	2009-03-08 00:06:01 +00:00
machine.c	A first attempt on supporting snapshots for the MIPS target.	2008-12-20 19:44:31 +00:00
mips-defs.h	Support for VR5432, and some of its special instructions. Original patch	2007-12-25 20:46:56 +00:00
op_helper.c	target-mips: implement FPU Flush-To-Zero mode	2009-03-28 22:22:40 +00:00
TODO	Move the active FPU registers into env again, and use more TCG registers	2008-09-18 11:57:27 +00:00
translate_init.c	target-mips: rename helpers from do_ to helper_	2009-03-08 00:06:01 +00:00
translate.c	target-mips: fix FPU in 64-bit mode	2009-03-28 22:22:50 +00:00