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5b50e790f9
Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/*
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* ARM gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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/* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
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whatever the target description contains. Due to a historical mishap
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the FPA registers appear in between core integer regs and the CPSR.
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We hack round this by giving the FPA regs zero size when talking to a
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newer gdb. */
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int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 16) {
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/* Core integer register. */
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return gdb_get_reg32(mem_buf, env->regs[n]);
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}
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if (n < 24) {
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/* FPA registers. */
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if (gdb_has_xml) {
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return 0;
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}
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memset(mem_buf, 0, 12);
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return 12;
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}
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switch (n) {
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case 24:
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/* FPA status register. */
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if (gdb_has_xml) {
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return 0;
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}
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return gdb_get_reg32(mem_buf, 0);
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case 25:
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/* CPSR */
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return gdb_get_reg32(mem_buf, cpsr_read(env));
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}
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/* Unknown register. */
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return 0;
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}
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int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint32_t tmp;
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tmp = ldl_p(mem_buf);
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/* Mask out low bit of PC to workaround gdb bugs. This will probably
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cause problems if we ever implement the Jazelle DBX extensions. */
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if (n == 15) {
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tmp &= ~1;
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}
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if (n < 16) {
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/* Core integer register. */
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env->regs[n] = tmp;
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return 4;
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}
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if (n < 24) { /* 16-23 */
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/* FPA registers (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 12;
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}
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switch (n) {
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case 24:
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/* FPA status register (ignored). */
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if (gdb_has_xml) {
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return 0;
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}
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return 4;
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case 25:
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/* CPSR */
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cpsr_write(env, tmp, 0xffffffff);
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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