mirror of
https://github.com/qemu/qemu.git
synced 2024-11-26 04:13:39 +08:00
52302d7274
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@715 c046a42c-6fe2-441c-8c8c-71466251a162
284 lines
7.8 KiB
C
284 lines
7.8 KiB
C
/*
|
|
* QEMU 16450 UART emulation
|
|
*
|
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
* in the Software without restriction, including without limitation the rights
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
* furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
* THE SOFTWARE.
|
|
*/
|
|
#include "vl.h"
|
|
|
|
//#define DEBUG_SERIAL
|
|
|
|
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
|
|
|
|
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
|
|
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
|
|
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
|
|
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
|
|
|
|
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
|
|
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
|
|
|
|
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
|
|
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
|
|
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
|
|
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
|
|
|
|
/*
|
|
* These are the definitions for the Modem Control Register
|
|
*/
|
|
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
|
|
#define UART_MCR_OUT2 0x08 /* Out2 complement */
|
|
#define UART_MCR_OUT1 0x04 /* Out1 complement */
|
|
#define UART_MCR_RTS 0x02 /* RTS complement */
|
|
#define UART_MCR_DTR 0x01 /* DTR complement */
|
|
|
|
/*
|
|
* These are the definitions for the Modem Status Register
|
|
*/
|
|
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
|
|
#define UART_MSR_RI 0x40 /* Ring Indicator */
|
|
#define UART_MSR_DSR 0x20 /* Data Set Ready */
|
|
#define UART_MSR_CTS 0x10 /* Clear to Send */
|
|
#define UART_MSR_DDCD 0x08 /* Delta DCD */
|
|
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
|
|
#define UART_MSR_DDSR 0x02 /* Delta DSR */
|
|
#define UART_MSR_DCTS 0x01 /* Delta CTS */
|
|
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
|
|
|
|
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
|
|
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
|
|
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
|
|
#define UART_LSR_FE 0x08 /* Frame error indicator */
|
|
#define UART_LSR_PE 0x04 /* Parity error indicator */
|
|
#define UART_LSR_OE 0x02 /* Overrun error indicator */
|
|
#define UART_LSR_DR 0x01 /* Receiver data ready */
|
|
|
|
struct SerialState {
|
|
uint8_t divider;
|
|
uint8_t rbr; /* receive register */
|
|
uint8_t ier;
|
|
uint8_t iir; /* read only */
|
|
uint8_t lcr;
|
|
uint8_t mcr;
|
|
uint8_t lsr; /* read only */
|
|
uint8_t msr;
|
|
uint8_t scr;
|
|
/* NOTE: this hidden state is necessary for tx irq generation as
|
|
it can be reset while reading iir */
|
|
int thr_ipending;
|
|
int irq;
|
|
int out_fd;
|
|
};
|
|
|
|
static void serial_update_irq(SerialState *s)
|
|
{
|
|
if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
|
|
s->iir = UART_IIR_RDI;
|
|
} else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
|
|
s->iir = UART_IIR_THRI;
|
|
} else {
|
|
s->iir = UART_IIR_NO_INT;
|
|
}
|
|
if (s->iir != UART_IIR_NO_INT) {
|
|
pic_set_irq(s->irq, 1);
|
|
} else {
|
|
pic_set_irq(s->irq, 0);
|
|
}
|
|
}
|
|
|
|
static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
SerialState *s = opaque;
|
|
unsigned char ch;
|
|
int ret;
|
|
|
|
addr &= 7;
|
|
#ifdef DEBUG_SERIAL
|
|
printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
|
|
#endif
|
|
switch(addr) {
|
|
default:
|
|
case 0:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
s->divider = (s->divider & 0xff00) | val;
|
|
} else {
|
|
s->thr_ipending = 0;
|
|
s->lsr &= ~UART_LSR_THRE;
|
|
serial_update_irq(s);
|
|
|
|
if (s->out_fd >= 0) {
|
|
ch = val;
|
|
do {
|
|
ret = write(s->out_fd, &ch, 1);
|
|
} while (ret != 1);
|
|
}
|
|
s->thr_ipending = 1;
|
|
s->lsr |= UART_LSR_THRE;
|
|
s->lsr |= UART_LSR_TEMT;
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 1:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
s->divider = (s->divider & 0x00ff) | (val << 8);
|
|
} else {
|
|
s->ier = val;
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 2:
|
|
break;
|
|
case 3:
|
|
s->lcr = val;
|
|
break;
|
|
case 4:
|
|
s->mcr = val;
|
|
break;
|
|
case 5:
|
|
break;
|
|
case 6:
|
|
s->msr = val;
|
|
break;
|
|
case 7:
|
|
s->scr = val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
|
|
{
|
|
SerialState *s = opaque;
|
|
uint32_t ret;
|
|
|
|
addr &= 7;
|
|
switch(addr) {
|
|
default:
|
|
case 0:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = s->divider & 0xff;
|
|
} else {
|
|
ret = s->rbr;
|
|
s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
serial_update_irq(s);
|
|
}
|
|
break;
|
|
case 1:
|
|
if (s->lcr & UART_LCR_DLAB) {
|
|
ret = (s->divider >> 8) & 0xff;
|
|
} else {
|
|
ret = s->ier;
|
|
}
|
|
break;
|
|
case 2:
|
|
ret = s->iir;
|
|
/* reset THR pending bit */
|
|
if ((ret & 0x7) == UART_IIR_THRI)
|
|
s->thr_ipending = 0;
|
|
serial_update_irq(s);
|
|
break;
|
|
case 3:
|
|
ret = s->lcr;
|
|
break;
|
|
case 4:
|
|
ret = s->mcr;
|
|
break;
|
|
case 5:
|
|
ret = s->lsr;
|
|
break;
|
|
case 6:
|
|
if (s->mcr & UART_MCR_LOOP) {
|
|
/* in loopback, the modem output pins are connected to the
|
|
inputs */
|
|
ret = (s->mcr & 0x0c) << 4;
|
|
ret |= (s->mcr & 0x02) << 3;
|
|
ret |= (s->mcr & 0x01) << 5;
|
|
} else {
|
|
ret = s->msr;
|
|
}
|
|
break;
|
|
case 7:
|
|
ret = s->scr;
|
|
break;
|
|
}
|
|
#ifdef DEBUG_SERIAL
|
|
printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
int serial_can_receive(SerialState *s)
|
|
{
|
|
return !(s->lsr & UART_LSR_DR);
|
|
}
|
|
|
|
void serial_receive_byte(SerialState *s, int ch)
|
|
{
|
|
s->rbr = ch;
|
|
s->lsr |= UART_LSR_DR;
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
void serial_receive_break(SerialState *s)
|
|
{
|
|
s->rbr = 0;
|
|
s->lsr |= UART_LSR_BI | UART_LSR_DR;
|
|
serial_update_irq(s);
|
|
}
|
|
|
|
static int serial_can_receive1(void *opaque)
|
|
{
|
|
SerialState *s = opaque;
|
|
return serial_can_receive(s);
|
|
}
|
|
|
|
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
SerialState *s = opaque;
|
|
serial_receive_byte(s, buf[0]);
|
|
}
|
|
|
|
/* If fd is zero, it means that the serial device uses the console */
|
|
SerialState *serial_init(int base, int irq, int fd)
|
|
{
|
|
SerialState *s;
|
|
|
|
s = qemu_mallocz(sizeof(SerialState));
|
|
if (!s)
|
|
return NULL;
|
|
s->irq = irq;
|
|
s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
|
|
s->iir = UART_IIR_NO_INT;
|
|
|
|
register_ioport_write(base, 8, 1, serial_ioport_write, s);
|
|
register_ioport_read(base, 8, 1, serial_ioport_read, s);
|
|
|
|
if (fd < 0) {
|
|
/* no associated device */
|
|
s->out_fd = -1;
|
|
} else if (fd != 0) {
|
|
qemu_add_fd_read_handler(fd, serial_can_receive1, serial_receive1, s);
|
|
s->out_fd = fd;
|
|
} else {
|
|
serial_console = s;
|
|
s->out_fd = 1;
|
|
}
|
|
return s;
|
|
}
|