mirror of
https://github.com/qemu/qemu.git
synced 2024-12-05 09:43:44 +08:00
403d7a2d73
We can now use cpu_reset() in place of cpu_state_reset() in main_cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Blue Swirl <blauwirbel@gmail.com>
999 lines
30 KiB
C
999 lines
30 KiB
C
/*
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* QEMU Sun4u/Sun4v System Emulator
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "apb_pci.h"
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#include "pc.h"
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#include "nvram.h"
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#include "fdc.h"
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#include "net.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "firmware_abi.h"
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#include "fw_cfg.h"
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#include "sysbus.h"
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#include "ide.h"
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#include "loader.h"
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#include "elf.h"
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#include "blockdev.h"
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#include "exec-memory.h"
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//#define DEBUG_IRQ
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//#define DEBUG_EBUS
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//#define DEBUG_TIMER
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#ifdef DEBUG_IRQ
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#define CPUIRQ_DPRINTF(fmt, ...) \
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do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define CPUIRQ_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_EBUS
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#define EBUS_DPRINTF(fmt, ...) \
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do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define EBUS_DPRINTF(fmt, ...)
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#endif
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#ifdef DEBUG_TIMER
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#define TIMER_DPRINTF(fmt, ...) \
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do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define TIMER_DPRINTF(fmt, ...)
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#endif
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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#define PROM_SIZE_MAX (4 * 1024 * 1024)
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#define PROM_VADDR 0x000ffd00000ULL
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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#define APB_MEM_BASE 0x1ff00000000ULL
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#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
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#define PROM_FILENAME "openbios-sparc64"
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#define NVRAM_SIZE 0x2000
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#define MAX_IDE_BUS 2
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#define BIOS_CFG_IOPORT 0x510
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#define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
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#define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
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#define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
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#define IVEC_MAX 0x30
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#define TICK_MAX 0x7fffffffffffffffULL
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struct hwdef {
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const char * const default_cpu_model;
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uint16_t machine_id;
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uint64_t prom_addr;
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uint64_t console_serial_base;
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};
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typedef struct EbusState {
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PCIDevice pci_dev;
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MemoryRegion bar0;
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MemoryRegion bar1;
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} EbusState;
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int DMA_get_channel_mode (int nchan)
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{
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return 0;
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}
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int DMA_read_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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int DMA_write_memory (int nchan, void *buf, int pos, int size)
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{
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return 0;
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}
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void DMA_hold_DREQ (int nchan) {}
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void DMA_release_DREQ (int nchan) {}
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void DMA_schedule(int nchan) {}
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void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
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{
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}
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void DMA_register_channel (int nchan,
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DMA_transfer_handler transfer_handler,
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void *opaque)
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{
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}
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static int fw_cfg_boot_set(void *opaque, const char *boot_device)
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{
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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return 0;
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}
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static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
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const char *arch, ram_addr_t RAM_size,
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const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth,
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const uint8_t *macaddr)
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{
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unsigned int i;
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uint32_t start, end;
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image));
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start = 0;
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// OpenBIOS nvram variables
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// Variable partition
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM;
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pstrcpy(part_header->name, sizeof(part_header->name), "system");
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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for (i = 0; i < nb_prom_envs; i++)
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end = OpenBIOS_set_var(image, end, prom_envs[i]);
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// End marker
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image[end++] = '\0';
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end = start + ((end - start + 15) & ~15);
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OpenBIOS_finish_partition(part_header, end - start);
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// free partition
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start = end;
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE;
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pstrcpy(part_header->name, sizeof(part_header->name), "free");
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end = 0x1fd0;
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OpenBIOS_finish_partition(part_header, end - start);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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return 0;
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}
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static uint64_t sun4u_load_kernel(const char *kernel_filename,
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const char *initrd_filename,
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ram_addr_t RAM_size, uint64_t *initrd_size,
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uint64_t *initrd_addr, uint64_t *kernel_addr,
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uint64_t *kernel_entry)
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{
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int linux_boot;
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unsigned int i;
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long kernel_size;
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uint8_t *ptr;
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uint64_t kernel_top;
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linux_boot = (kernel_filename != NULL);
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kernel_size = 0;
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if (linux_boot) {
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int bswap_needed;
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#ifdef BSWAP_NEEDED
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bswap_needed = 1;
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#else
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bswap_needed = 0;
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#endif
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kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry,
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kernel_addr, &kernel_top, 1, ELF_MACHINE, 0);
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if (kernel_size < 0) {
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*kernel_addr = KERNEL_LOAD_ADDR;
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*kernel_entry = KERNEL_LOAD_ADDR;
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kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
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TARGET_PAGE_SIZE);
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}
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename,
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KERNEL_LOAD_ADDR,
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RAM_size - KERNEL_LOAD_ADDR);
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd above kernel */
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*initrd_size = 0;
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if (initrd_filename) {
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*initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
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*initrd_size = load_image_targphys(initrd_filename,
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*initrd_addr,
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RAM_size - *initrd_addr);
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if ((int)*initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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if (*initrd_size > 0) {
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for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
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ptr = rom_ptr(*kernel_addr + i);
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if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
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stl_p(ptr + 24, *initrd_addr + *kernel_addr);
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stl_p(ptr + 28, *initrd_size);
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break;
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}
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}
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}
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}
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return kernel_size;
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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uint32_t pil = env->pil_in |
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(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
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/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
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if (env->ivec_status & 0x20) {
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return;
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}
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/* check if TM or SM in SOFTINT are set
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setting these also causes interrupt 14 */
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if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
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pil |= 1 << 14;
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}
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/* The bit corresponding to psrpil is (1<< psrpil), the next bit
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is (2 << psrpil). */
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if (pil < (2 << env->psrpil)){
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if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
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env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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return;
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}
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if (cpu_interrupts_enabled(env)) {
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unsigned int i;
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for (i = 15; i > env->psrpil; i--) {
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if (pil & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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int new_interrupt = TT_EXTINT | i;
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if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
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&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
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CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
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"current %x >= pending %x\n",
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env->tl, cpu_tsptr(env)->tt, new_interrupt);
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} else if (old_interrupt != new_interrupt) {
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env->interrupt_index = new_interrupt;
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CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
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old_interrupt, new_interrupt);
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
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CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
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"current interrupt %x\n",
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pil, env->pil_in, env->softint, env->interrupt_index);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(CPUSPARCState *env)
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{
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env->halted = 0;
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cpu_check_irqs(env);
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qemu_cpu_kick(env);
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}
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static void cpu_set_ivec_irq(void *opaque, int irq, int level)
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{
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CPUSPARCState *env = opaque;
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if (level) {
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if (!(env->ivec_status & 0x20)) {
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CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
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env->halted = 0;
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env->interrupt_index = TT_IVEC;
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env->ivec_status |= 0x20;
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env->ivec_data[0] = (0x1f << 6) | irq;
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env->ivec_data[1] = 0;
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env->ivec_data[2] = 0;
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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} else {
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if (env->ivec_status & 0x20) {
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CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
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env->ivec_status &= ~0x20;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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}
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typedef struct ResetData {
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SPARCCPU *cpu;
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uint64_t prom_addr;
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} ResetData;
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void cpu_put_timer(QEMUFile *f, CPUTimer *s)
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{
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qemu_put_be32s(f, &s->frequency);
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qemu_put_be32s(f, &s->disabled);
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qemu_put_be64s(f, &s->disabled_mask);
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qemu_put_sbe64s(f, &s->clock_offset);
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qemu_put_timer(f, s->qtimer);
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}
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void cpu_get_timer(QEMUFile *f, CPUTimer *s)
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{
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qemu_get_be32s(f, &s->frequency);
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qemu_get_be32s(f, &s->disabled);
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qemu_get_be64s(f, &s->disabled_mask);
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qemu_get_sbe64s(f, &s->clock_offset);
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qemu_get_timer(f, s->qtimer);
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}
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static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
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QEMUBHFunc *cb, uint32_t frequency,
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uint64_t disabled_mask)
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{
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CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
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timer->name = name;
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timer->frequency = frequency;
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timer->disabled_mask = disabled_mask;
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timer->disabled = 1;
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timer->clock_offset = qemu_get_clock_ns(vm_clock);
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timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
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return timer;
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}
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static void cpu_timer_reset(CPUTimer *timer)
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{
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timer->disabled = 1;
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timer->clock_offset = qemu_get_clock_ns(vm_clock);
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qemu_del_timer(timer->qtimer);
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}
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUSPARCState *env = &s->cpu->env;
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static unsigned int nr_resets;
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cpu_reset(CPU(s->cpu));
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cpu_timer_reset(env->tick);
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cpu_timer_reset(env->stick);
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cpu_timer_reset(env->hstick);
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env->gregs[1] = 0; // Memory start
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env->gregs[2] = ram_size; // Memory size
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env->gregs[3] = 0; // Machine description XXX
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if (nr_resets++ == 0) {
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/* Power on reset */
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env->pc = s->prom_addr + 0x20ULL;
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} else {
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env->pc = s->prom_addr + 0x40ULL;
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}
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env->npc = env->pc + 4;
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}
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static void tick_irq(void *opaque)
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{
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->tick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("tick: fire\n");
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}
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env->softint |= SOFTINT_TIMER;
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cpu_kick_irq(env);
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}
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static void stick_irq(void *opaque)
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{
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->stick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("stick: fire\n");
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(env);
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}
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static void hstick_irq(void *opaque)
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{
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CPUSPARCState *env = opaque;
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CPUTimer* timer = env->hstick;
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if (timer->disabled) {
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CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
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return;
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} else {
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CPUIRQ_DPRINTF("hstick: fire\n");
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}
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env->softint |= SOFTINT_STIMER;
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cpu_kick_irq(env);
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}
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static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
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{
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return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
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}
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static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
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{
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return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
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}
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void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
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{
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uint64_t real_count = count & ~timer->disabled_mask;
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uint64_t disabled_bit = count & timer->disabled_mask;
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int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
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cpu_to_timer_ticks(real_count, timer->frequency);
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TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
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timer->name, real_count,
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timer->disabled?"disabled":"enabled", timer);
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timer->disabled = disabled_bit ? 1 : 0;
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timer->clock_offset = vm_clock_offset;
|
|
}
|
|
|
|
uint64_t cpu_tick_get_count(CPUTimer *timer)
|
|
{
|
|
uint64_t real_count = timer_to_cpu_ticks(
|
|
qemu_get_clock_ns(vm_clock) - timer->clock_offset,
|
|
timer->frequency);
|
|
|
|
TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
|
|
timer->name, real_count,
|
|
timer->disabled?"disabled":"enabled", timer);
|
|
|
|
if (timer->disabled)
|
|
real_count |= timer->disabled_mask;
|
|
|
|
return real_count;
|
|
}
|
|
|
|
void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
|
|
{
|
|
int64_t now = qemu_get_clock_ns(vm_clock);
|
|
|
|
uint64_t real_limit = limit & ~timer->disabled_mask;
|
|
timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
|
|
|
|
int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
|
|
timer->clock_offset;
|
|
|
|
if (expires < now) {
|
|
expires = now + 1;
|
|
}
|
|
|
|
TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
|
|
"called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
|
|
timer->name, real_limit,
|
|
timer->disabled?"disabled":"enabled",
|
|
timer, limit,
|
|
timer_to_cpu_ticks(now - timer->clock_offset,
|
|
timer->frequency),
|
|
timer_to_cpu_ticks(expires - now, timer->frequency));
|
|
|
|
if (!real_limit) {
|
|
TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
|
|
timer->name);
|
|
qemu_del_timer(timer->qtimer);
|
|
} else if (timer->disabled) {
|
|
qemu_del_timer(timer->qtimer);
|
|
} else {
|
|
qemu_mod_timer(timer->qtimer, expires);
|
|
}
|
|
}
|
|
|
|
static void isa_irq_handler(void *opaque, int n, int level)
|
|
{
|
|
static const int isa_irq_to_ivec[16] = {
|
|
[1] = 0x29, /* keyboard */
|
|
[4] = 0x2b, /* serial */
|
|
[6] = 0x27, /* floppy */
|
|
[7] = 0x22, /* parallel */
|
|
[12] = 0x2a, /* mouse */
|
|
};
|
|
qemu_irq *irqs = opaque;
|
|
int ivec;
|
|
|
|
assert(n < 16);
|
|
ivec = isa_irq_to_ivec[n];
|
|
EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
|
|
if (ivec) {
|
|
qemu_set_irq(irqs[ivec], level);
|
|
}
|
|
}
|
|
|
|
/* EBUS (Eight bit bus) bridge */
|
|
static ISABus *
|
|
pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
|
|
{
|
|
qemu_irq *isa_irq;
|
|
PCIDevice *pci_dev;
|
|
ISABus *isa_bus;
|
|
|
|
pci_dev = pci_create_simple(bus, devfn, "ebus");
|
|
isa_bus = DO_UPCAST(ISABus, qbus,
|
|
qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
|
|
isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
|
|
isa_bus_irqs(isa_bus, isa_irq);
|
|
return isa_bus;
|
|
}
|
|
|
|
static int
|
|
pci_ebus_init1(PCIDevice *pci_dev)
|
|
{
|
|
EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
|
|
|
|
isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
|
|
|
|
pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
|
|
pci_dev->config[0x05] = 0x00;
|
|
pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
|
|
pci_dev->config[0x07] = 0x03; // status = medium devsel
|
|
pci_dev->config[0x09] = 0x00; // programming i/f
|
|
pci_dev->config[0x0D] = 0x0a; // latency_timer
|
|
|
|
isa_mmio_setup(&s->bar0, 0x1000000);
|
|
pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
|
|
isa_mmio_setup(&s->bar1, 0x800000);
|
|
pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
|
|
return 0;
|
|
}
|
|
|
|
static void ebus_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->init = pci_ebus_init1;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_EBUS;
|
|
k->revision = 0x01;
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
|
}
|
|
|
|
static TypeInfo ebus_info = {
|
|
.name = "ebus",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(EbusState),
|
|
.class_init = ebus_class_init,
|
|
};
|
|
|
|
typedef struct PROMState {
|
|
SysBusDevice busdev;
|
|
MemoryRegion prom;
|
|
} PROMState;
|
|
|
|
static uint64_t translate_prom_address(void *opaque, uint64_t addr)
|
|
{
|
|
target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
|
|
return addr + *base_addr - PROM_VADDR;
|
|
}
|
|
|
|
/* Boot PROM (OpenBIOS) */
|
|
static void prom_init(target_phys_addr_t addr, const char *bios_name)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
char *filename;
|
|
int ret;
|
|
|
|
dev = qdev_create(NULL, "openprom");
|
|
qdev_init_nofail(dev);
|
|
s = sysbus_from_qdev(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
|
|
/* load boot prom */
|
|
if (bios_name == NULL) {
|
|
bios_name = PROM_FILENAME;
|
|
}
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
if (filename) {
|
|
ret = load_elf(filename, translate_prom_address, &addr,
|
|
NULL, NULL, NULL, 1, ELF_MACHINE, 0);
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
|
|
}
|
|
g_free(filename);
|
|
} else {
|
|
ret = -1;
|
|
}
|
|
if (ret < 0 || ret > PROM_SIZE_MAX) {
|
|
fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
static int prom_init1(SysBusDevice *dev)
|
|
{
|
|
PROMState *s = FROM_SYSBUS(PROMState, dev);
|
|
|
|
memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
|
|
vmstate_register_ram_global(&s->prom);
|
|
memory_region_set_readonly(&s->prom, true);
|
|
sysbus_init_mmio(dev, &s->prom);
|
|
return 0;
|
|
}
|
|
|
|
static Property prom_properties[] = {
|
|
{/* end of property list */},
|
|
};
|
|
|
|
static void prom_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = prom_init1;
|
|
dc->props = prom_properties;
|
|
}
|
|
|
|
static TypeInfo prom_info = {
|
|
.name = "openprom",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(PROMState),
|
|
.class_init = prom_class_init,
|
|
};
|
|
|
|
|
|
typedef struct RamDevice
|
|
{
|
|
SysBusDevice busdev;
|
|
MemoryRegion ram;
|
|
uint64_t size;
|
|
} RamDevice;
|
|
|
|
/* System RAM */
|
|
static int ram_init1(SysBusDevice *dev)
|
|
{
|
|
RamDevice *d = FROM_SYSBUS(RamDevice, dev);
|
|
|
|
memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
|
|
vmstate_register_ram_global(&d->ram);
|
|
sysbus_init_mmio(dev, &d->ram);
|
|
return 0;
|
|
}
|
|
|
|
static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *s;
|
|
RamDevice *d;
|
|
|
|
/* allocate RAM */
|
|
dev = qdev_create(NULL, "memory");
|
|
s = sysbus_from_qdev(dev);
|
|
|
|
d = FROM_SYSBUS(RamDevice, s);
|
|
d->size = RAM_size;
|
|
qdev_init_nofail(dev);
|
|
|
|
sysbus_mmio_map(s, 0, addr);
|
|
}
|
|
|
|
static Property ram_properties[] = {
|
|
DEFINE_PROP_UINT64("size", RamDevice, size, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ram_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = ram_init1;
|
|
dc->props = ram_properties;
|
|
}
|
|
|
|
static TypeInfo ram_info = {
|
|
.name = "memory",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(RamDevice),
|
|
.class_init = ram_class_init,
|
|
};
|
|
|
|
static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
|
|
{
|
|
SPARCCPU *cpu;
|
|
CPUSPARCState *env;
|
|
ResetData *reset_info;
|
|
|
|
uint32_t tick_frequency = 100*1000000;
|
|
uint32_t stick_frequency = 100*1000000;
|
|
uint32_t hstick_frequency = 100*1000000;
|
|
|
|
if (cpu_model == NULL) {
|
|
cpu_model = hwdef->default_cpu_model;
|
|
}
|
|
cpu = cpu_sparc_init(cpu_model);
|
|
if (cpu == NULL) {
|
|
fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
|
exit(1);
|
|
}
|
|
env = &cpu->env;
|
|
|
|
env->tick = cpu_timer_create("tick", env, tick_irq,
|
|
tick_frequency, TICK_NPT_MASK);
|
|
|
|
env->stick = cpu_timer_create("stick", env, stick_irq,
|
|
stick_frequency, TICK_INT_DIS);
|
|
|
|
env->hstick = cpu_timer_create("hstick", env, hstick_irq,
|
|
hstick_frequency, TICK_INT_DIS);
|
|
|
|
reset_info = g_malloc0(sizeof(ResetData));
|
|
reset_info->cpu = cpu;
|
|
reset_info->prom_addr = hwdef->prom_addr;
|
|
qemu_register_reset(main_cpu_reset, reset_info);
|
|
|
|
return cpu;
|
|
}
|
|
|
|
static void sun4uv_init(MemoryRegion *address_space_mem,
|
|
ram_addr_t RAM_size,
|
|
const char *boot_devices,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model,
|
|
const struct hwdef *hwdef)
|
|
{
|
|
SPARCCPU *cpu;
|
|
CPUSPARCState *env;
|
|
M48t59State *nvram;
|
|
unsigned int i;
|
|
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
|
|
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
|
ISABus *isa_bus;
|
|
qemu_irq *ivec_irqs, *pbm_irqs;
|
|
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
|
|
DriveInfo *fd[MAX_FD];
|
|
void *fw_cfg;
|
|
|
|
/* init CPUs */
|
|
cpu = cpu_devinit(cpu_model, hwdef);
|
|
env = &cpu->env;
|
|
|
|
/* set up devices */
|
|
ram_init(0, RAM_size);
|
|
|
|
prom_init(hwdef->prom_addr, bios_name);
|
|
|
|
ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
|
|
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
|
|
&pci_bus3, &pbm_irqs);
|
|
pci_vga_init(pci_bus);
|
|
|
|
// XXX Should be pci_bus3
|
|
isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
|
|
|
|
i = 0;
|
|
if (hwdef->console_serial_base) {
|
|
serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
|
|
NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
|
|
i++;
|
|
}
|
|
for(; i < MAX_SERIAL_PORTS; i++) {
|
|
if (serial_hds[i]) {
|
|
serial_isa_init(isa_bus, i, serial_hds[i]);
|
|
}
|
|
}
|
|
|
|
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
|
|
if (parallel_hds[i]) {
|
|
parallel_init(isa_bus, i, parallel_hds[i]);
|
|
}
|
|
}
|
|
|
|
for(i = 0; i < nb_nics; i++)
|
|
pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
|
|
|
|
ide_drive_get(hd, MAX_IDE_BUS);
|
|
|
|
pci_cmd646_ide_init(pci_bus, hd, 1);
|
|
|
|
isa_create_simple(isa_bus, "i8042");
|
|
for(i = 0; i < MAX_FD; i++) {
|
|
fd[i] = drive_get(IF_FLOPPY, 0, i);
|
|
}
|
|
fdctrl_init_isa(isa_bus, fd);
|
|
nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
|
|
|
|
initrd_size = 0;
|
|
initrd_addr = 0;
|
|
kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
|
|
ram_size, &initrd_size, &initrd_addr,
|
|
&kernel_addr, &kernel_entry);
|
|
|
|
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
|
kernel_addr, kernel_size,
|
|
kernel_cmdline,
|
|
initrd_addr, initrd_size,
|
|
/* XXX: need an option to load a NVRAM image */
|
|
0,
|
|
graphic_width, graphic_height, graphic_depth,
|
|
(uint8_t *)&nd_table[0].macaddr);
|
|
|
|
fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
|
|
if (kernel_cmdline) {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
|
|
strlen(kernel_cmdline) + 1);
|
|
fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
|
|
(uint8_t*)strdup(kernel_cmdline),
|
|
strlen(kernel_cmdline) + 1);
|
|
} else {
|
|
fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
|
|
}
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
|
|
fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
|
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
|
|
fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
|
|
|
|
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
|
|
}
|
|
|
|
enum {
|
|
sun4u_id = 0,
|
|
sun4v_id = 64,
|
|
niagara_id,
|
|
};
|
|
|
|
static const struct hwdef hwdefs[] = {
|
|
/* Sun4u generic PC-like machine */
|
|
{
|
|
.default_cpu_model = "TI UltraSparc IIi",
|
|
.machine_id = sun4u_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
/* Sun4v generic PC-like machine */
|
|
{
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
|
.machine_id = sun4v_id,
|
|
.prom_addr = 0x1fff0000000ULL,
|
|
.console_serial_base = 0,
|
|
},
|
|
/* Sun4v generic Niagara machine */
|
|
{
|
|
.default_cpu_model = "Sun UltraSparc T1",
|
|
.machine_id = niagara_id,
|
|
.prom_addr = 0xfff0000000ULL,
|
|
.console_serial_base = 0xfff0c2c000ULL,
|
|
},
|
|
};
|
|
|
|
/* Sun4u hardware initialisation */
|
|
static void sun4u_init(ram_addr_t RAM_size,
|
|
const char *boot_devices,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
|
}
|
|
|
|
/* Sun4v hardware initialisation */
|
|
static void sun4v_init(ram_addr_t RAM_size,
|
|
const char *boot_devices,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
|
}
|
|
|
|
/* Niagara hardware initialisation */
|
|
static void niagara_init(ram_addr_t RAM_size,
|
|
const char *boot_devices,
|
|
const char *kernel_filename, const char *kernel_cmdline,
|
|
const char *initrd_filename, const char *cpu_model)
|
|
{
|
|
sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
|
|
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
|
}
|
|
|
|
static QEMUMachine sun4u_machine = {
|
|
.name = "sun4u",
|
|
.desc = "Sun4u platform",
|
|
.init = sun4u_init,
|
|
.max_cpus = 1, // XXX for now
|
|
.is_default = 1,
|
|
};
|
|
|
|
static QEMUMachine sun4v_machine = {
|
|
.name = "sun4v",
|
|
.desc = "Sun4v platform",
|
|
.init = sun4v_init,
|
|
.max_cpus = 1, // XXX for now
|
|
};
|
|
|
|
static QEMUMachine niagara_machine = {
|
|
.name = "Niagara",
|
|
.desc = "Sun4v platform, Niagara",
|
|
.init = niagara_init,
|
|
.max_cpus = 1, // XXX for now
|
|
};
|
|
|
|
static void sun4u_register_types(void)
|
|
{
|
|
type_register_static(&ebus_info);
|
|
type_register_static(&prom_info);
|
|
type_register_static(&ram_info);
|
|
}
|
|
|
|
static void sun4u_machine_init(void)
|
|
{
|
|
qemu_register_machine(&sun4u_machine);
|
|
qemu_register_machine(&sun4v_machine);
|
|
qemu_register_machine(&niagara_machine);
|
|
}
|
|
|
|
type_init(sun4u_register_types)
|
|
machine_init(sun4u_machine_init);
|