Alex Bennée e65a5f227d tcg/aarch64: limit mul_vec size ... In AdvSIMD we can only do 32x32 integer multiples although SVE is capable of larger 64 bit multiples. As a result we can end up generating invalid opcodes. Fix this by only reprting we can emit mul vector ops if the size is small enough. Fixes a crash on: sve-all-short-v8.3+sve@vq3/insn_mul_z_zi___INC.risu.bin When running on AArch64 hardware. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20180719154248.29669-1-alex.bennee@linaro.org> [rth: Removed the tcg_debug_assert -- there are plenty of other cases that we do not diagnose within the insn encoding helpers.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2018-07-19 09:07:31 -07:00
..
tcg-target.h	tcg/aarch64: Add vector operations	2018-02-08 15:54:08 +00:00
tcg-target.inc.c	tcg/aarch64: limit mul_vec size	2018-07-19 09:07:31 -07:00
tcg-target.opc.h	tcg/aarch64: Add vector operations	2018-02-08 15:54:08 +00:00