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Xtensa ISA got specification for 64-bit floating point registers and opcodes, see ISA, 4.3.11 "Floating point coprocessor option". Add 64-bit FP registers. Although 64-bit floating point is currently not supported by xtensa translator, these registers need to be reported to gdb with proper size, otherwise it wouldn't find other registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> |
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core-dc232b | ||
core-dc233c | ||
core-fsf | ||
core-dc232b.c | ||
core-dc233c.c | ||
core-fsf.c | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
gdbstub.c | ||
helper.c | ||
helper.h | ||
import_core.sh | ||
Makefile.objs | ||
op_helper.c | ||
overlay_tool.h | ||
translate.c | ||
xtensa-semi.c |