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00b941e581
Change breakpoint_invalidate() argument to CPUState alongside.
Since all targets now assign a softmmu-only field, we can drop helpers
cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
Prepares for changing cpu_memory_rw_debug() argument to CPUState.
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
289 lines
9.8 KiB
C
289 lines
9.8 KiB
C
/*
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* MicroBlaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "qemu/host-utils.h"
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#define D(x)
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#define DMMU(x)
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#if defined(CONFIG_USER_ONLY)
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void mb_cpu_do_interrupt(CPUState *cs)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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env->exception_index = -1;
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env->res_addr = RES_ADDR_NONE;
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env->regs[14] = env->sregs[SR_PC];
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}
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int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
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int mmu_idx)
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{
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MicroBlazeCPU *cpu = mb_env_get_cpu(env);
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env->exception_index = 0xaa;
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cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
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return 1;
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}
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#else /* !CONFIG_USER_ONLY */
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int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
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int mmu_idx)
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{
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unsigned int hit;
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unsigned int mmu_available;
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int r = 1;
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int prot;
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mmu_available = 0;
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if (env->pvr.regs[0] & PVR0_USE_MMU) {
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mmu_available = 1;
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if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
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&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
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mmu_available = 0;
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}
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}
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/* Translate if the MMU is available and enabled. */
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if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
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target_ulong vaddr, paddr;
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struct microblaze_mmu_lookup lu;
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hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
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if (hit) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
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mmu_idx, vaddr, paddr, lu.prot));
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tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
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r = 0;
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} else {
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env->sregs[SR_EAR] = address;
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DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address));
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switch (lu.err) {
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case ERR_PROT:
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env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
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env->sregs[SR_ESR] |= (rw == 1) << 10;
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break;
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case ERR_MISS:
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env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
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env->sregs[SR_ESR] |= (rw == 1) << 10;
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break;
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default:
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abort();
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break;
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}
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if (env->exception_index == EXCP_MMU) {
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cpu_abort(env, "recursive faults\n");
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}
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/* TLB miss. */
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env->exception_index = EXCP_MMU;
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}
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} else {
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/* MMU disabled or not available. */
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address &= TARGET_PAGE_MASK;
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prot = PAGE_BITS;
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tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
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r = 0;
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}
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return r;
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}
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void mb_cpu_do_interrupt(CPUState *cs)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint32_t t;
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/* IMM flag cannot propagate across a branch and into the dslot. */
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assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
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assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
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/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
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env->res_addr = RES_ADDR_NONE;
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switch (env->exception_index) {
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case EXCP_HW_EXCP:
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if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
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qemu_log("Exception raised on system without exceptions!\n");
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return;
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}
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env->regs[17] = env->sregs[SR_PC] + 4;
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env->sregs[SR_ESR] &= ~(1 << 12);
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/* Exception breaks branch + dslot sequence? */
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if (env->iflags & D_FLAG) {
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env->sregs[SR_ESR] |= 1 << 12 ;
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env->sregs[SR_BTR] = env->btarget;
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}
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/* Disable the MMU. */
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t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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env->sregs[SR_MSR] |= t;
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/* Exception in progress. */
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env->sregs[SR_MSR] |= MSR_EIP;
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qemu_log_mask(CPU_LOG_INT,
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"hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
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env->sregs[SR_PC], env->sregs[SR_EAR],
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env->sregs[SR_ESR], env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->iflags &= ~(IMM_FLAG | D_FLAG);
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env->sregs[SR_PC] = cpu->base_vectors + 0x20;
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break;
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case EXCP_MMU:
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env->regs[17] = env->sregs[SR_PC];
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env->sregs[SR_ESR] &= ~(1 << 12);
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/* Exception breaks branch + dslot sequence? */
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if (env->iflags & D_FLAG) {
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D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
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env->sregs[SR_ESR] |= 1 << 12 ;
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env->sregs[SR_BTR] = env->btarget;
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/* Reexecute the branch. */
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env->regs[17] -= 4;
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/* was the branch immprefixed?. */
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if (env->bimm) {
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qemu_log_mask(CPU_LOG_INT,
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"bimm exception at pc=%x iflags=%x\n",
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env->sregs[SR_PC], env->iflags);
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env->regs[17] -= 4;
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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}
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} else if (env->iflags & IMM_FLAG) {
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D(qemu_log("IMM_FLAG set at exception\n"));
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env->regs[17] -= 4;
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}
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/* Disable the MMU. */
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t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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env->sregs[SR_MSR] |= t;
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/* Exception in progress. */
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env->sregs[SR_MSR] |= MSR_EIP;
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qemu_log_mask(CPU_LOG_INT,
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"exception at pc=%x ear=%x iflags=%x\n",
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env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->iflags &= ~(IMM_FLAG | D_FLAG);
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env->sregs[SR_PC] = cpu->base_vectors + 0x20;
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break;
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case EXCP_IRQ:
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assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
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assert(env->sregs[SR_MSR] & MSR_IE);
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assert(!(env->iflags & D_FLAG));
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t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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#if 0
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#include "disas/disas.h"
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/* Useful instrumentation when debugging interrupt issues in either
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the models or in sw. */
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{
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const char *sym;
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sym = lookup_symbol(env->sregs[SR_PC]);
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if (sym
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&& (!strcmp("netif_rx", sym)
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|| !strcmp("process_backlog", sym))) {
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qemu_log(
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"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
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env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
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sym);
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log_cpu_state(cs, 0);
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}
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}
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#endif
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qemu_log_mask(CPU_LOG_INT,
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"interrupt at pc=%x msr=%x %x iflags=%x\n",
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env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
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env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
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| MSR_UM | MSR_IE);
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env->sregs[SR_MSR] |= t;
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env->regs[14] = env->sregs[SR_PC];
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env->sregs[SR_PC] = cpu->base_vectors + 0x10;
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//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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break;
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case EXCP_BREAK:
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case EXCP_HW_BREAK:
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assert(!(env->iflags & IMM_FLAG));
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assert(!(env->iflags & D_FLAG));
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t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
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qemu_log_mask(CPU_LOG_INT,
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"break at pc=%x msr=%x %x iflags=%x\n",
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env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
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log_cpu_state_mask(CPU_LOG_INT, cs, 0);
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env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
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env->sregs[SR_MSR] |= t;
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env->sregs[SR_MSR] |= MSR_BIP;
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if (env->exception_index == EXCP_HW_BREAK) {
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env->regs[16] = env->sregs[SR_PC];
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env->sregs[SR_MSR] |= MSR_BIP;
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env->sregs[SR_PC] = cpu->base_vectors + 0x18;
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} else
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env->sregs[SR_PC] = env->btarget;
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break;
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default:
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cpu_abort(env, "unhandled exception type=%d\n",
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env->exception_index);
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break;
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}
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}
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hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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target_ulong vaddr, paddr = 0;
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struct microblaze_mmu_lookup lu;
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unsigned int hit;
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if (env->sregs[SR_MSR] & MSR_VM) {
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hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
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if (hit) {
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vaddr = addr & TARGET_PAGE_MASK;
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paddr = lu.paddr + vaddr - lu.vaddr;
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} else
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paddr = 0; /* ???. */
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} else
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paddr = addr & TARGET_PAGE_MASK;
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return paddr;
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}
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#endif
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