Sergey Fedorov 5d98bf8f38 target-arm: Fix CPU breakpoint handling ... A QEMU breakpoint match is not definitely an architectural breakpoint match. If an exception is generated unconditionally during translation, it is hardly possible to ignore it in the debug exception handler. Generate a call to a helper to check CPU breakpoints and raise an exception only if any breakpoint matches architecturally. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2015-10-16 14:48:56 +01:00
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arm_ldst.h	softmmu: introduce cpu_ldst.h	2014-06-05 16:10:33 +02:00
arm-semi.c	target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block	2015-09-07 10:39:28 +01:00
cpu64.c	target-arm: Fix REVIDR reset value	2015-06-15 18:06:08 +01:00
cpu-qom.h	target-arm: Refactor CPU affinity handling	2015-09-07 10:39:31 +01:00
cpu.c	qdev: Protect device-list-properties against broken devices	2015-10-09 15:25:57 +02:00
cpu.h	target-arm: implement arm_debug_target_el()	2015-10-16 13:34:02 +01:00
crypto_helper.c	crypto: move built-in AES implementation into crypto/	2015-07-07 12:04:13 +02:00
gdbstub64.c	target-arm/gdbstub64.c: remove useless 'break' statement.	2014-04-17 21:34:06 +01:00
gdbstub.c	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
helper-a64.c	target-arm: Use new revbit functions	2015-09-15 07:45:33 -07:00
helper-a64.h	target-arm: A64: Implement CRC instructions	2014-06-09 16:06:12 +01:00
helper.c	target-arm: Add MDCR_EL2	2015-10-16 13:13:48 +01:00
helper.h	target-arm: Fix CPU breakpoint handling	2015-10-16 14:48:56 +01:00
internals.h	target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction	2015-09-07 10:39:28 +01:00
iwmmxt_helper.c	target-arm: Delete unused iwmmxt_msadb helper	2014-06-09 16:06:12 +01:00
kvm32.c	target-arm: Refactor CPU affinity handling	2015-09-07 10:39:31 +01:00
kvm64.c	target-arm: Refactor CPU affinity handling	2015-09-07 10:39:31 +01:00
kvm_arm.h	hw/intc: Initial implementation of vGICv3	2015-09-24 01:29:37 +01:00
kvm-consts.h	target-arm/kvm64: Add cortex-a53 cpu support	2015-06-15 18:06:08 +01:00
kvm-stub.c	target-arm: kvm: Differentiate registers based on write-back levels	2015-07-21 11:18:45 +01:00
kvm.c	arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create()	2015-09-24 01:29:37 +01:00
machine.c	hw/intc: Initial implementation of vGICv3	2015-09-24 01:29:37 +01:00
Makefile.objs	target-arm: add emulation of PSCI calls for system emulation	2014-10-24 12:19:13 +01:00
neon_helper.c	target-arm: add support for v8 VMULL.P64 instruction	2014-06-09 16:06:11 +01:00
op_addsub.h	Correct spelling of licensed	2011-07-23 11:26:12 -05:00
op_helper.c	target-arm: Fix CPU breakpoint handling	2015-10-16 14:48:56 +01:00
psci.c	target-arm: Use the kernel's idea of MPIDR if we're using KVM	2015-06-15 18:06:09 +01:00
translate-a64.c	target-arm: Fix CPU breakpoint handling	2015-10-16 14:48:56 +01:00
translate.c	target-arm: Fix CPU breakpoint handling	2015-10-16 14:48:56 +01:00
translate.h	tcg: Remove gen_intermediate_code_pc	2015-10-07 20:36:52 +11:00