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db1015e92e
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
423 lines
14 KiB
C
423 lines
14 KiB
C
/*
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* QEMU i440FX PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/range.h"
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#include "hw/i386/pc.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/i440fx.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "qapi/visitor.h"
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#include "qemu/error-report.h"
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#include "qom/object.h"
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/*
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* I440FX chipset data sheet.
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* https://wiki.qemu.org/File:29054901.pdf
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*/
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typedef struct I440FXState I440FXState;
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#define I440FX_PCI_HOST_BRIDGE(obj) \
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OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
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struct I440FXState {
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PCIHostState parent_obj;
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Range pci_hole;
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uint64_t pci_hole64_size;
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bool pci_hole64_fix;
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uint32_t short_root_bus;
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};
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#define I440FX_PAM 0x59
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#define I440FX_PAM_SIZE 7
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#define I440FX_SMRAM 0x72
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/* Keep it 2G to comply with older win32 guests */
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#define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
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/* Older coreboot versions (4.0 and older) read a config register that doesn't
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* exist in real hardware, to get the RAM size from QEMU.
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*/
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#define I440FX_COREBOOT_RAM_SIZE 0x57
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static void i440fx_update_memory_mappings(PCII440FXState *d)
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{
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int i;
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PCIDevice *pd = PCI_DEVICE(d);
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memory_region_transaction_begin();
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for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
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pam_update(&d->pam_regions[i], i,
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pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
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}
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memory_region_set_enabled(&d->smram_region,
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!(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
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memory_region_set_enabled(&d->smram,
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pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
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memory_region_transaction_commit();
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}
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static void i440fx_write_config(PCIDevice *dev,
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uint32_t address, uint32_t val, int len)
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{
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PCII440FXState *d = I440FX_PCI_DEVICE(dev);
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(dev, address, val, len);
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if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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range_covers_byte(address, len, I440FX_SMRAM)) {
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i440fx_update_memory_mappings(d);
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}
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}
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static int i440fx_post_load(void *opaque, int version_id)
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{
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PCII440FXState *d = opaque;
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i440fx_update_memory_mappings(d);
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return 0;
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}
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static const VMStateDescription vmstate_i440fx = {
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.name = "I440FX",
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.version_id = 3,
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.minimum_version_id = 3,
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.post_load = i440fx_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
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/* Used to be smm_enabled, which was basically always zero because
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* SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
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*/
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VMSTATE_UNUSED(1),
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VMSTATE_END_OF_LIST()
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}
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};
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static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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uint64_t val64;
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uint32_t value;
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val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
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value = val64;
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assert(value == val64);
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visit_type_uint32(v, name, &value, errp);
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}
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static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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uint64_t val64;
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uint32_t value;
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val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
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value = val64;
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assert(value == val64);
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visit_type_uint32(v, name, &value, errp);
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}
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/*
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* The 64bit PCI hole start is set by the Guest firmware
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* as the address of the first 64bit PCI MEM resource.
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* If no PCI device has resources on the 64bit area,
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* the 64bit PCI hole will start after "over 4G RAM" and the
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* reserved space for memory hotplug if any.
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*/
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static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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Range w64;
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uint64_t value;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_lob(&w64);
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if (!value && s->pci_hole64_fix) {
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value = pc_pci_hole64_start();
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}
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return value;
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}
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static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
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const char *name,
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void *opaque, Error **errp)
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{
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uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
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visit_type_uint64(v, name, &hole64_start, errp);
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}
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/*
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* The 64bit PCI hole end is set by the Guest firmware
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* as the address of the last 64bit PCI MEM resource.
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* Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
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* that can be configured by the user.
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*/
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static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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PCIHostState *h = PCI_HOST_BRIDGE(obj);
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I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
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Range w64;
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uint64_t value, hole64_end;
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pci_bus_get_w64_range(h->bus, &w64);
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value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
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hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
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if (s->pci_hole64_fix && value < hole64_end) {
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value = hole64_end;
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}
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visit_type_uint64(v, name, &value, errp);
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}
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static void i440fx_pcihost_initfn(Object *obj)
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{
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PCIHostState *s = PCI_HOST_BRIDGE(obj);
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memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4);
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memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
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"pci-conf-data", 4);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
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i440fx_pcihost_get_pci_hole_start,
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NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
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i440fx_pcihost_get_pci_hole_end,
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NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
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i440fx_pcihost_get_pci_hole64_start,
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NULL, NULL, NULL);
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object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
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i440fx_pcihost_get_pci_hole64_end,
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NULL, NULL, NULL);
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}
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static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
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{
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PCIHostState *s = PCI_HOST_BRIDGE(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
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sysbus_init_ioports(sbd, 0xcf8, 4);
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sysbus_add_io(sbd, 0xcfc, &s->data_mem);
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sysbus_init_ioports(sbd, 0xcfc, 4);
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/* register i440fx 0xcf8 port as coalesced pio */
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memory_region_set_flush_coalesced(&s->data_mem);
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memory_region_add_coalescing(&s->conf_mem, 0, 4);
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}
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static void i440fx_realize(PCIDevice *dev, Error **errp)
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{
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dev->config[I440FX_SMRAM] = 0x02;
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if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
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warn_report("i440fx doesn't support emulated iommu");
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}
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}
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PCIBus *i440fx_init(const char *host_type, const char *pci_type,
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PCII440FXState **pi440fx_state,
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MemoryRegion *address_space_mem,
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MemoryRegion *address_space_io,
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ram_addr_t ram_size,
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ram_addr_t below_4g_mem_size,
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ram_addr_t above_4g_mem_size,
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MemoryRegion *pci_address_space,
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MemoryRegion *ram_memory)
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{
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DeviceState *dev;
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PCIBus *b;
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PCIDevice *d;
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PCIHostState *s;
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PCII440FXState *f;
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unsigned i;
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I440FXState *i440fx;
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dev = qdev_new(host_type);
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s = PCI_HOST_BRIDGE(dev);
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b = pci_root_bus_new(dev, NULL, pci_address_space,
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address_space_io, 0, TYPE_PCI_BUS);
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s->bus = b;
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object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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d = pci_create_simple(b, 0, pci_type);
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*pi440fx_state = I440FX_PCI_DEVICE(d);
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f = *pi440fx_state;
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f->system_memory = address_space_mem;
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f->pci_address_space = pci_address_space;
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f->ram_memory = ram_memory;
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i440fx = I440FX_PCI_HOST_BRIDGE(dev);
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range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
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IO_APIC_DEFAULT_ADDRESS - 1);
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/* setup pci memory mapping */
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pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
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f->pci_address_space);
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/* if *disabled* show SMRAM to all CPUs */
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memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
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f->pci_address_space, 0xa0000, 0x20000);
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memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
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&f->smram_region, 1);
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memory_region_set_enabled(&f->smram_region, true);
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/* smram, as seen by SMM CPUs */
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memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB);
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memory_region_set_enabled(&f->smram, true);
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memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
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f->ram_memory, 0xa0000, 0x20000);
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memory_region_set_enabled(&f->low_smram, true);
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memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
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object_property_add_const_link(qdev_get_machine(), "smram",
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OBJECT(&f->smram));
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init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
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&f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
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for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
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init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
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&f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
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PAM_EXPAN_SIZE);
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}
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ram_size = ram_size / 8 / 1024 / 1024;
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if (ram_size > 255) {
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ram_size = 255;
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}
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d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
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i440fx_update_memory_mappings(f);
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return b;
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}
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PCIBus *find_i440fx(void)
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{
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PCIHostState *s = OBJECT_CHECK(PCIHostState,
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object_resolve_path("/machine/i440fx", NULL),
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TYPE_PCI_HOST_BRIDGE);
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return s ? s->bus : NULL;
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}
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static void i440fx_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = i440fx_realize;
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k->config_write = i440fx_write_config;
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k->vendor_id = PCI_VENDOR_ID_INTEL;
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k->device_id = PCI_DEVICE_ID_INTEL_82441;
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k->revision = 0x02;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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dc->desc = "Host bridge";
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dc->vmsd = &vmstate_i440fx;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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dc->hotpluggable = false;
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}
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static const TypeInfo i440fx_info = {
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.name = TYPE_I440FX_PCI_DEVICE,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCII440FXState),
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.class_init = i440fx_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
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PCIBus *rootbus)
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{
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I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
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/* For backwards compat with old device paths */
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if (s->short_root_bus) {
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return "0000";
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}
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return "0000:00";
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}
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static Property i440fx_props[] = {
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DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
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pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
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DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
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DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
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hc->root_bus_path = i440fx_pcihost_root_bus_path;
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dc->realize = i440fx_pcihost_realize;
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dc->fw_name = "pci";
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device_class_set_props(dc, i440fx_props);
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/* Reason: needs to be wired up by pc_init1 */
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dc->user_creatable = false;
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}
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static const TypeInfo i440fx_pcihost_info = {
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.name = TYPE_I440FX_PCI_HOST_BRIDGE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(I440FXState),
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.instance_init = i440fx_pcihost_initfn,
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.class_init = i440fx_pcihost_class_init,
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};
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static void i440fx_register_types(void)
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{
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type_register_static(&i440fx_info);
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type_register_static(&i440fx_pcihost_info);
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}
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type_init(i440fx_register_types)
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