Cédric Le Goater fcdf2c5945 aspeed/smc: handle SPI flash Command mode ... The Aspeed SMC controllers have a mode (Command mode) in which accesses to the flash content are no different than doing MMIOs. The controller generates all the necessary commands to load (or store) data in memory. However, accesses are restricted to the segment window assigned the the flash module by the controller. This window is defined by the Segment Address Register. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-8-git-send-email-clg@kaod.org [PMM: Deleted now-unused aspeed_smc_is_usermode() function] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2017-01-20 11:15:08 +00:00
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aspeed_smc.c	aspeed/smc: handle SPI flash Command mode	2017-01-20 11:15:08 +00:00
imx_spi.c	hw/ssi/imx_spi.c: Remove MSGDATA register support	2017-01-09 11:50:23 +00:00
Makefile.objs	STM32F2xx: Add the SPI device	2016-10-04 13:28:07 +01:00
omap_spi.c	arm devices: Clean up includes	2016-01-29 15:07:25 +00:00
pl022.c	hw: explicitly include qemu/log.h	2016-05-19 16:42:29 +02:00
ssi.c	ssi: change ssi_slave_init to be a realize ops	2016-07-04 13:15:22 +01:00
stm32f2xx_spi.c	STM32F2xx: Add the SPI device	2016-10-04 13:28:07 +01:00
xilinx_spi.c	arm: Clean up includes	2016-01-29 15:07:23 +00:00
xilinx_spips.c	xilinx: fix buffer overflow on realize	2016-10-24 15:27:20 +02:00