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7827168471
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
945 lines
29 KiB
C
945 lines
29 KiB
C
/*
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* Sparc CPU init helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu/module.h"
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#include "qemu/qemu-print.h"
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#include "exec/exec-all.h"
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#include "hw/qdev-properties.h"
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#include "qapi/visitor.h"
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//#define DEBUG_FEATURES
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static void sparc_cpu_reset(DeviceState *dev)
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{
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CPUState *s = CPU(dev);
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SPARCCPU *cpu = SPARC_CPU(s);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
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CPUSPARCState *env = &cpu->env;
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scc->parent_reset(dev);
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memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
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env->cwp = 0;
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#ifndef TARGET_SPARC64
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env->wim = 1;
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#endif
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env->regwptr = env->regbase + (env->cwp * 16);
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CC_OP = CC_OP_FLAGS;
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#if defined(CONFIG_USER_ONLY)
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#ifdef TARGET_SPARC64
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env->cleanwin = env->nwindows - 2;
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env->cansave = env->nwindows - 2;
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env->pstate = PS_RMO | PS_PEF | PS_IE;
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env->asi = 0x82; /* Primary no-fault */
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#endif
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#else
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#if !defined(TARGET_SPARC64)
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env->psret = 0;
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env->psrs = 1;
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env->psrps = 1;
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#endif
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#ifdef TARGET_SPARC64
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env->pstate = PS_PRIV | PS_RED | PS_PEF;
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if (!cpu_has_hypervisor(env)) {
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env->pstate |= PS_AG;
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}
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env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
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env->tl = env->maxtl;
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env->gl = 2;
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cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
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env->lsu = 0;
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#else
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env->mmuregs[0] &= ~(MMU_E | MMU_NF);
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env->mmuregs[0] |= env->def.mmu_bm;
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#endif
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env->pc = 0;
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env->npc = env->pc + 4;
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#endif
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env->cache_control = 0;
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}
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static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
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int pil = env->interrupt_index & 0xf;
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int type = env->interrupt_index & 0xf0;
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if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
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cs->exception_index = env->interrupt_index;
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sparc_cpu_do_interrupt(cs);
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return true;
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}
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}
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}
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return false;
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}
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static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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info->print_insn = print_insn_sparc;
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#ifdef TARGET_SPARC64
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info->mach = bfd_mach_sparc_v9b;
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#endif
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}
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static void
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cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
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{
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GlobalProperty *prop = g_new0(typeof(*prop), 1);
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prop->driver = typename;
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prop->property = g_strdup(name);
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prop->value = g_strdup(val);
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qdev_prop_register_global(prop);
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}
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/* Parse "+feature,-feature,feature=foo" CPU feature string */
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static void sparc_cpu_parse_features(const char *typename, char *features,
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Error **errp)
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{
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GList *l, *plus_features = NULL, *minus_features = NULL;
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char *featurestr; /* Single 'key=value" string being parsed */
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static bool cpu_globals_initialized;
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if (cpu_globals_initialized) {
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return;
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}
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cpu_globals_initialized = true;
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if (!features) {
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return;
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}
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for (featurestr = strtok(features, ",");
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featurestr;
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featurestr = strtok(NULL, ",")) {
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const char *name;
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const char *val = NULL;
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char *eq = NULL;
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/* Compatibility syntax: */
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if (featurestr[0] == '+') {
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plus_features = g_list_append(plus_features,
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g_strdup(featurestr + 1));
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continue;
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} else if (featurestr[0] == '-') {
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minus_features = g_list_append(minus_features,
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g_strdup(featurestr + 1));
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continue;
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}
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eq = strchr(featurestr, '=');
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name = featurestr;
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if (eq) {
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*eq++ = 0;
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val = eq;
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/*
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* Temporarily, only +feat/-feat will be supported
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* for boolean properties until we remove the
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* minus-overrides-plus semantics and just follow
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* the order options appear on the command-line.
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*
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* TODO: warn if user is relying on minus-override-plus semantics
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* TODO: remove minus-override-plus semantics after
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* warning for a few releases
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*/
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if (!strcasecmp(val, "on") ||
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!strcasecmp(val, "off") ||
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!strcasecmp(val, "true") ||
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!strcasecmp(val, "false")) {
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error_setg(errp, "Boolean properties in format %s=%s"
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" are not supported", name, val);
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return;
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}
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} else {
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error_setg(errp, "Unsupported property format: %s", name);
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return;
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}
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cpu_add_feat_as_prop(typename, name, val);
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}
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for (l = plus_features; l; l = l->next) {
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const char *name = l->data;
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cpu_add_feat_as_prop(typename, name, "on");
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}
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g_list_free_full(plus_features, g_free);
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for (l = minus_features; l; l = l->next) {
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const char *name = l->data;
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cpu_add_feat_as_prop(typename, name, "off");
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}
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g_list_free_full(minus_features, g_free);
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}
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
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{
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#if !defined(TARGET_SPARC64)
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env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
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#endif
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}
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static const sparc_def_t sparc_defs[] = {
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#ifdef TARGET_SPARC64
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{
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.name = "Fujitsu Sparc64",
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.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 4,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 III",
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.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 5,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 IV",
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.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 V",
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.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc I",
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.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc II",
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.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIi",
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.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIe",
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.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III",
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.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III Cu",
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.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IIIi",
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.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV",
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.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_4,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV+",
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.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
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},
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{
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.name = "Sun UltraSparc IIIi+",
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.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc T1",
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "Sun UltraSparc T2",
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "NEC UltraSparc I",
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.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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#else
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{
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x0000003f,
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.nwindows = 7,
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.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
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CPU_FEATURE_FMUL,
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},
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{
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc IIep",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x04000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016bff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "TI SuperSparc 51",
|
|
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
|
.fpu_version = 0 << 17,
|
|
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.mxcc_version = 0x00000104,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "TI SuperSparc 60", /* STP1020APGA */
|
|
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
|
.fpu_version = 0 << 17,
|
|
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "TI SuperSparc 61",
|
|
.iu_version = 0x44000000, /* SuperSPARC 3.x */
|
|
.fpu_version = 0 << 17,
|
|
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.mxcc_version = 0x00000104,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "TI SuperSparc II",
|
|
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
|
|
.fpu_version = 0 << 17,
|
|
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
|
|
.mmu_bm = 0x00002000,
|
|
.mmu_ctpr_mask = 0xffffffc0,
|
|
.mmu_cxr_mask = 0x0000ffff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.mxcc_version = 0x00000104,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES,
|
|
},
|
|
{
|
|
.name = "LEON2",
|
|
.iu_version = 0xf2000000,
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
.mmu_version = 0xf2000000,
|
|
.mmu_bm = 0x00004000,
|
|
.mmu_ctpr_mask = 0x007ffff0,
|
|
.mmu_cxr_mask = 0x0000003f,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
|
},
|
|
{
|
|
.name = "LEON3",
|
|
.iu_version = 0xf3000000,
|
|
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
|
.mmu_version = 0xf3000000,
|
|
.mmu_bm = 0x00000000,
|
|
.mmu_ctpr_mask = 0xfffffffc,
|
|
.mmu_cxr_mask = 0x000000ff,
|
|
.mmu_sfsr_mask = 0xffffffff,
|
|
.mmu_trcr_mask = 0xffffffff,
|
|
.nwindows = 8,
|
|
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
|
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
|
|
CPU_FEATURE_CASA,
|
|
},
|
|
#endif
|
|
};
|
|
|
|
static const char * const feature_name[] = {
|
|
"float",
|
|
"float128",
|
|
"swap",
|
|
"mul",
|
|
"div",
|
|
"flush",
|
|
"fsqrt",
|
|
"fmul",
|
|
"vis1",
|
|
"vis2",
|
|
"fsmuld",
|
|
"hypv",
|
|
"cmt",
|
|
"gl",
|
|
};
|
|
|
|
static void print_features(uint32_t features, const char *prefix)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
|
if (feature_name[i] && (features & (1 << i))) {
|
|
if (prefix) {
|
|
qemu_printf("%s", prefix);
|
|
}
|
|
qemu_printf("%s ", feature_name[i]);
|
|
}
|
|
}
|
|
}
|
|
|
|
void sparc_cpu_list(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
|
qemu_printf("Sparc %16s IU " TARGET_FMT_lx
|
|
" FPU %08x MMU %08x NWINS %d ",
|
|
sparc_defs[i].name,
|
|
sparc_defs[i].iu_version,
|
|
sparc_defs[i].fpu_version,
|
|
sparc_defs[i].mmu_version,
|
|
sparc_defs[i].nwindows);
|
|
print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
|
|
print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
|
|
qemu_printf("\n");
|
|
}
|
|
qemu_printf("Default CPU feature flags (use '-' to remove): ");
|
|
print_features(CPU_DEFAULT_FEATURES, NULL);
|
|
qemu_printf("\n");
|
|
qemu_printf("Available CPU feature flags (use '+' to add): ");
|
|
print_features(~CPU_DEFAULT_FEATURES, NULL);
|
|
qemu_printf("\n");
|
|
qemu_printf("Numerical features (use '=' to set): iu_version "
|
|
"fpu_version mmu_version nwindows\n");
|
|
}
|
|
|
|
static void cpu_print_cc(FILE *f, uint32_t cc)
|
|
{
|
|
qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
|
|
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
|
|
cc & PSR_CARRY ? 'C' : '-');
|
|
}
|
|
|
|
#ifdef TARGET_SPARC64
|
|
#define REGS_PER_LINE 4
|
|
#else
|
|
#define REGS_PER_LINE 8
|
|
#endif
|
|
|
|
void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
CPUSPARCState *env = &cpu->env;
|
|
int i, x;
|
|
|
|
qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
|
|
env->npc);
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
if (i % REGS_PER_LINE == 0) {
|
|
qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
|
|
}
|
|
qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
for (x = 0; x < 3; x++) {
|
|
for (i = 0; i < 8; i++) {
|
|
if (i % REGS_PER_LINE == 0) {
|
|
qemu_fprintf(f, "%%%c%d-%d: ",
|
|
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
|
|
i, i + REGS_PER_LINE - 1);
|
|
}
|
|
qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
|
|
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
if (flags & CPU_DUMP_FPU) {
|
|
for (i = 0; i < TARGET_DPREGS; i++) {
|
|
if ((i & 3) == 0) {
|
|
qemu_fprintf(f, "%%f%02d: ", i * 2);
|
|
}
|
|
qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
|
|
if ((i & 3) == 3) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef TARGET_SPARC64
|
|
qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
|
(unsigned)cpu_get_ccr(env));
|
|
cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
|
|
qemu_fprintf(f, " xcc: ");
|
|
cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
|
qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
|
|
env->psrpil, env->gl);
|
|
qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
|
|
TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
|
|
qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
|
"cleanwin: %d cwp: %d\n",
|
|
env->cansave, env->canrestore, env->otherwin, env->wstate,
|
|
env->cleanwin, env->nwindows - 1 - env->cwp);
|
|
qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
|
|
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
|
|
|
#else
|
|
qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
|
cpu_print_cc(f, cpu_get_psr(env));
|
|
qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
|
|
env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
|
|
env->wim);
|
|
qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
|
|
env->fsr, env->y);
|
|
#endif
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
|
|
static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
cpu->env.pc = value;
|
|
cpu->env.npc = value + 4;
|
|
}
|
|
|
|
static void sparc_cpu_synchronize_from_tb(CPUState *cs,
|
|
const TranslationBlock *tb)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
cpu->env.pc = tb->pc;
|
|
cpu->env.npc = tb->cs_base;
|
|
}
|
|
|
|
static bool sparc_cpu_has_work(CPUState *cs)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
cpu_interrupts_enabled(env);
|
|
}
|
|
|
|
static char *sparc_cpu_type_name(const char *cpu_model)
|
|
{
|
|
char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
|
|
char *s = name;
|
|
|
|
/* SPARC cpu model names happen to have whitespaces,
|
|
* as type names shouldn't have spaces replace them with '-'
|
|
*/
|
|
while ((s = strchr(s, ' '))) {
|
|
*s = '-';
|
|
}
|
|
|
|
return name;
|
|
}
|
|
|
|
static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
|
|
{
|
|
ObjectClass *oc;
|
|
char *typename;
|
|
|
|
typename = sparc_cpu_type_name(cpu_model);
|
|
oc = object_class_by_name(typename);
|
|
g_free(typename);
|
|
return oc;
|
|
}
|
|
|
|
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
|
|
Error *local_err = NULL;
|
|
SPARCCPU *cpu = SPARC_CPU(dev);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
#if defined(CONFIG_USER_ONLY)
|
|
if ((env->def.features & CPU_FEATURE_FLOAT)) {
|
|
env->def.features |= CPU_FEATURE_FLOAT128;
|
|
}
|
|
#endif
|
|
|
|
env->version = env->def.iu_version;
|
|
env->fsr = env->def.fpu_version;
|
|
env->nwindows = env->def.nwindows;
|
|
#if !defined(TARGET_SPARC64)
|
|
env->mmuregs[0] |= env->def.mmu_version;
|
|
cpu_sparc_set_id(env, 0);
|
|
env->mxccregs[7] |= env->def.mxcc_version;
|
|
#else
|
|
env->mmu_version = env->def.mmu_version;
|
|
env->maxtl = env->def.maxtl;
|
|
env->version |= env->def.maxtl << 8;
|
|
env->version |= env->def.nwindows - 1;
|
|
#endif
|
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
if (local_err != NULL) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
qemu_init_vcpu(cs);
|
|
|
|
scc->parent_realize(dev, errp);
|
|
}
|
|
|
|
static void sparc_cpu_initfn(Object *obj)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
cpu_set_cpustate_pointers(cpu);
|
|
|
|
if (scc->cpu_def) {
|
|
env->def = *scc->cpu_def;
|
|
}
|
|
}
|
|
|
|
static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
int64_t value = cpu->env.def.nwindows;
|
|
|
|
visit_type_int(v, name, &value, errp);
|
|
}
|
|
|
|
static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
|
|
void *opaque, Error **errp)
|
|
{
|
|
const int64_t min = MIN_NWINDOWS;
|
|
const int64_t max = MAX_NWINDOWS;
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
int64_t value;
|
|
|
|
if (!visit_type_int(v, name, &value, errp)) {
|
|
return;
|
|
}
|
|
|
|
if (value < min || value > max) {
|
|
error_setg(errp, "Property %s.%s doesn't take value %" PRId64
|
|
" (minimum: %" PRId64 ", maximum: %" PRId64 ")",
|
|
object_get_typename(obj), name ? name : "null",
|
|
value, min, max);
|
|
return;
|
|
}
|
|
cpu->env.def.nwindows = value;
|
|
}
|
|
|
|
static PropertyInfo qdev_prop_nwindows = {
|
|
.name = "int",
|
|
.get = sparc_get_nwindows,
|
|
.set = sparc_set_nwindows,
|
|
};
|
|
|
|
static Property sparc_cpu_properties[] = {
|
|
DEFINE_PROP_BIT("float", SPARCCPU, env.def.features, 0, false),
|
|
DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features, 1, false),
|
|
DEFINE_PROP_BIT("swap", SPARCCPU, env.def.features, 2, false),
|
|
DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features, 3, false),
|
|
DEFINE_PROP_BIT("div", SPARCCPU, env.def.features, 4, false),
|
|
DEFINE_PROP_BIT("flush", SPARCCPU, env.def.features, 5, false),
|
|
DEFINE_PROP_BIT("fsqrt", SPARCCPU, env.def.features, 6, false),
|
|
DEFINE_PROP_BIT("fmul", SPARCCPU, env.def.features, 7, false),
|
|
DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features, 8, false),
|
|
DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features, 9, false),
|
|
DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features, 10, false),
|
|
DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features, 11, false),
|
|
DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features, 12, false),
|
|
DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features, 13, false),
|
|
DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
|
|
qdev_prop_uint64, target_ulong),
|
|
DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
|
|
DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
|
|
DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
|
|
qdev_prop_nwindows, uint32_t),
|
|
DEFINE_PROP_END_OF_LIST()
|
|
};
|
|
|
|
#ifdef CONFIG_TCG
|
|
#include "hw/core/tcg-cpu-ops.h"
|
|
|
|
static struct TCGCPUOps sparc_tcg_ops = {
|
|
.initialize = sparc_tcg_init,
|
|
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
|
|
.cpu_exec_interrupt = sparc_cpu_exec_interrupt,
|
|
.tlb_fill = sparc_cpu_tlb_fill,
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
.do_interrupt = sparc_cpu_do_interrupt,
|
|
.do_transaction_failed = sparc_cpu_do_transaction_failed,
|
|
.do_unaligned_access = sparc_cpu_do_unaligned_access,
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
};
|
|
#endif /* CONFIG_TCG */
|
|
|
|
static void sparc_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
|
|
&scc->parent_realize);
|
|
device_class_set_props(dc, sparc_cpu_properties);
|
|
|
|
device_class_set_parent_reset(dc, sparc_cpu_reset, &scc->parent_reset);
|
|
|
|
cc->class_by_name = sparc_cpu_class_by_name;
|
|
cc->parse_features = sparc_cpu_parse_features;
|
|
cc->has_work = sparc_cpu_has_work;
|
|
cc->dump_state = sparc_cpu_dump_state;
|
|
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
|
|
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
|
|
#endif
|
|
cc->set_pc = sparc_cpu_set_pc;
|
|
cc->gdb_read_register = sparc_cpu_gdb_read_register;
|
|
cc->gdb_write_register = sparc_cpu_gdb_write_register;
|
|
#ifndef CONFIG_USER_ONLY
|
|
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
|
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cc->vmsd = &vmstate_sparc_cpu;
|
|
#endif
|
|
cc->disas_set_info = cpu_sparc_disas_set_info;
|
|
|
|
#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
|
|
cc->gdb_num_core_regs = 86;
|
|
#else
|
|
cc->gdb_num_core_regs = 72;
|
|
#endif
|
|
cc->tcg_ops = &sparc_tcg_ops;
|
|
}
|
|
|
|
static const TypeInfo sparc_cpu_type_info = {
|
|
.name = TYPE_SPARC_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(SPARCCPU),
|
|
.instance_init = sparc_cpu_initfn,
|
|
.abstract = true,
|
|
.class_size = sizeof(SPARCCPUClass),
|
|
.class_init = sparc_cpu_class_init,
|
|
};
|
|
|
|
static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
scc->cpu_def = data;
|
|
}
|
|
|
|
static void sparc_register_cpudef_type(const struct sparc_def_t *def)
|
|
{
|
|
char *typename = sparc_cpu_type_name(def->name);
|
|
TypeInfo ti = {
|
|
.name = typename,
|
|
.parent = TYPE_SPARC_CPU,
|
|
.class_init = sparc_cpu_cpudef_class_init,
|
|
.class_data = (void *)def,
|
|
};
|
|
|
|
type_register(&ti);
|
|
g_free(typename);
|
|
}
|
|
|
|
static void sparc_cpu_register_types(void)
|
|
{
|
|
int i;
|
|
|
|
type_register_static(&sparc_cpu_type_info);
|
|
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
|
sparc_register_cpudef_type(&sparc_defs[i]);
|
|
}
|
|
}
|
|
|
|
type_init(sparc_cpu_register_types)
|