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ec150c7e09
Back in 2016, we discussed[1] rules for headers, and these were
generally liked:
1. Have a carefully curated header that's included everywhere first. We
got that already thanks to Peter: osdep.h.
2. Headers should normally include everything they need beyond osdep.h.
If exceptions are needed for some reason, they must be documented in
the header. If all that's needed from a header is typedefs, put
those into qemu/typedefs.h instead of including the header.
3. Cyclic inclusion is forbidden.
This patch gets include/ closer to obeying 2.
It's actually extracted from my "[RFC] Baby steps towards saner
headers" series[2], which demonstrates a possible path towards
checking 2 automatically. It passes the RFC test there.
[1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org>
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html
[2] Message-Id: <20190711122827.18970-1-armbru@redhat.com>
https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg02715.html
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20190812052359.30071-2-armbru@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
#ifndef ALLWINNER_A10_PIT_H
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#define ALLWINNER_A10_PIT_H
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#include "hw/ptimer.h"
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#include "hw/sysbus.h"
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#define TYPE_AW_A10_PIT "allwinner-A10-timer"
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#define AW_A10_PIT(obj) OBJECT_CHECK(AwA10PITState, (obj), TYPE_AW_A10_PIT)
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#define AW_A10_PIT_TIMER_NR 6
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#define AW_A10_PIT_TIMER_IRQ 0x1
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#define AW_A10_PIT_WDOG_IRQ 0x100
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#define AW_A10_PIT_TIMER_IRQ_EN 0
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#define AW_A10_PIT_TIMER_IRQ_ST 0x4
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#define AW_A10_PIT_TIMER_CONTROL 0x0
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#define AW_A10_PIT_TIMER_EN 0x1
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#define AW_A10_PIT_TIMER_RELOAD 0x2
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#define AW_A10_PIT_TIMER_MODE 0x80
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#define AW_A10_PIT_TIMER_INTERVAL 0x4
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#define AW_A10_PIT_TIMER_COUNT 0x8
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#define AW_A10_PIT_WDOG_CONTROL 0x90
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#define AW_A10_PIT_WDOG_MODE 0x94
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#define AW_A10_PIT_COUNT_CTL 0xa0
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#define AW_A10_PIT_COUNT_RL_EN 0x2
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#define AW_A10_PIT_COUNT_CLR_EN 0x1
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#define AW_A10_PIT_COUNT_LO 0xa4
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#define AW_A10_PIT_COUNT_HI 0xa8
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#define AW_A10_PIT_TIMER_BASE 0x10
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#define AW_A10_PIT_TIMER_BASE_END \
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(AW_A10_PIT_TIMER_BASE * 6 + AW_A10_PIT_TIMER_COUNT)
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#define AW_A10_PIT_DEFAULT_CLOCK 0x4
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typedef struct AwA10PITState AwA10PITState;
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typedef struct AwA10TimerContext {
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AwA10PITState *container;
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int index;
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} AwA10TimerContext;
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struct AwA10PITState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq irq[AW_A10_PIT_TIMER_NR];
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ptimer_state * timer[AW_A10_PIT_TIMER_NR];
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AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR];
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MemoryRegion iomem;
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uint32_t clk_freq[4];
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uint32_t irq_enable;
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uint32_t irq_status;
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uint32_t control[AW_A10_PIT_TIMER_NR];
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uint32_t interval[AW_A10_PIT_TIMER_NR];
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uint32_t count[AW_A10_PIT_TIMER_NR];
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uint32_t watch_dog_mode;
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uint32_t watch_dog_control;
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uint32_t count_lo;
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uint32_t count_hi;
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uint32_t count_ctl;
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};
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#endif
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