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From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and:
7. System Control
7.1. Overview
A10 embeds a high-speed SRAM which has been split into five segments.
See detailed memory mapping in following table:
Area Address Size (Bytes)
A1 0x00000000-0x00003FFF 16K
A2 0x00004000-0x00007FFF 16K
A3 0x00008000-0x0000B3FF 13K
A4 0x0000B400-0x0000BFFF 3K
Since for emulation purpose we don't need the segmentations, we simply define
the 'A' area as a single 48KB SRAM.
We don't implement the following others areas:
- 'B': 'Secure RAM' (64K),
- 'C': Debug/ISP SRAM
- 'D': USB SRAM
(qemu) info mtree
address-space: memory
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-000000000000bfff (prio 0, ram): sram A
0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl
0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac
0000000001c18000-0000000001c18fff (prio 0, i/o): ahci
0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci
0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic
0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer
0000000001c28000-0000000001c2801f (prio 0, i/o): serial
0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram
Reported-by: Charlie Smurthwaite <charlie@atech.media>
Tested-by: Charlie Smurthwaite <charlie@atech.media>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20190104142921.878-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
43 lines
1002 B
C
43 lines
1002 B
C
#ifndef ALLWINNER_H_
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "hw/char/serial.h"
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#include "hw/arm/arm.h"
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#include "hw/timer/allwinner-a10-pit.h"
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#include "hw/intc/allwinner-a10-pic.h"
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#include "hw/net/allwinner_emac.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "sysemu/sysemu.h"
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#define AW_A10_PIC_REG_BASE 0x01c20400
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#define AW_A10_PIT_REG_BASE 0x01c20c00
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#define AW_A10_UART0_REG_BASE 0x01c28000
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#define AW_A10_EMAC_BASE 0x01c0b000
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#define AW_A10_SATA_BASE 0x01c18000
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#define AW_A10_SDRAM_BASE 0x40000000
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#define TYPE_AW_A10 "allwinner-a10"
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#define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10)
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typedef struct AwA10State {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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ARMCPU cpu;
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qemu_irq irq[AW_A10_PIC_INT_NR];
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AwA10PITState timer;
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AwA10PICState intc;
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AwEmacState emac;
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AllwinnerAHCIState sata;
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MemoryRegion sram_a;
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} AwA10State;
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#define ALLWINNER_H_
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#endif
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