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https://github.com/qemu/qemu.git
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2c85fad022
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
/*
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* Generic PKUnity SoC machine and board descriptor
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu-common.h"
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#include "ui/console.h"
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#include "elf.h"
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#include "exec/address-spaces.h"
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#include "hw/sysbus.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/i386/pc.h"
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#include "sysemu/qtest.h"
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h"
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#define KERNEL_LOAD_ADDR 0x03000000
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#define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */
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static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
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{
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UniCore32CPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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assert(irq == 0);
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void puv3_soc_init(CPUUniCore32State *env)
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{
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qemu_irq cpu_intc, irqs[PUV3_IRQS_NR];
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DeviceState *dev;
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MemoryRegion *i8042 = g_new(MemoryRegion, 1);
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int i;
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/* Initialize interrupt controller */
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cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler,
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uc32_env_get_cpu(env), 0);
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dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc);
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for (i = 0; i < PUV3_IRQS_NR; i++) {
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irqs[i] = qdev_get_gpio_in(dev, i);
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}
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/* Initialize minimal necessary devices for kernel booting */
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sysbus_create_simple("puv3_pm", PUV3_PM_BASE, NULL);
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sysbus_create_simple("puv3_dma", PUV3_DMA_BASE, NULL);
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sysbus_create_simple("puv3_ost", PUV3_OST_BASE, irqs[PUV3_IRQS_OST0]);
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sysbus_create_varargs("puv3_gpio", PUV3_GPIO_BASE,
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irqs[PUV3_IRQS_GPIOLOW0], irqs[PUV3_IRQS_GPIOLOW1],
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irqs[PUV3_IRQS_GPIOLOW2], irqs[PUV3_IRQS_GPIOLOW3],
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irqs[PUV3_IRQS_GPIOLOW4], irqs[PUV3_IRQS_GPIOLOW5],
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irqs[PUV3_IRQS_GPIOLOW6], irqs[PUV3_IRQS_GPIOLOW7],
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irqs[PUV3_IRQS_GPIOHIGH], NULL);
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/* Keyboard (i8042), mouse disabled for nographic */
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i8042_mm_init(irqs[PUV3_IRQS_PS2_KBD], NULL, i8042, PUV3_REGS_OFFSET, 4);
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memory_region_add_subregion(get_system_memory(), PUV3_PS2_BASE, i8042);
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}
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static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
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{
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MemoryRegion *ram_memory = g_new(MemoryRegion, 1);
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/* SDRAM at address zero. */
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memory_region_init_ram(ram_memory, NULL, "puv3.ram", ram_size,
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&error_abort);
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vmstate_register_ram_global(ram_memory);
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memory_region_add_subregion(get_system_memory(), 0, ram_memory);
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}
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static const GraphicHwOps no_ops;
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static void puv3_load_kernel(const char *kernel_filename)
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{
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int size;
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if (kernel_filename == NULL && qtest_enabled()) {
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return;
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}
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assert(kernel_filename != NULL);
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/* only zImage format supported */
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size = load_image_targphys(kernel_filename, KERNEL_LOAD_ADDR,
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KERNEL_MAX_SIZE);
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if (size < 0) {
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hw_error("Load kernel error: '%s'\n", kernel_filename);
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}
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/* cheat curses that we have a graphic console, only under ocd console */
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graphic_console_init(NULL, 0, &no_ops, NULL);
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}
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static void puv3_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *cpu_model = machine->cpu_model;
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const char *kernel_filename = machine->kernel_filename;
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const char *initrd_filename = machine->initrd_filename;
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CPUUniCore32State *env;
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UniCore32CPU *cpu;
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if (initrd_filename) {
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hw_error("Please use kernel built-in initramdisk.\n");
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}
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if (!cpu_model) {
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cpu_model = "UniCore-II";
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}
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cpu = uc32_cpu_init(cpu_model);
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if (!cpu) {
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hw_error("Unable to find CPU definition\n");
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}
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env = &cpu->env;
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puv3_soc_init(env);
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puv3_board_init(env, ram_size);
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puv3_load_kernel(kernel_filename);
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}
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static QEMUMachine puv3_machine = {
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.name = "puv3",
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.desc = "PKUnity Version-3 based on UniCore32",
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.init = puv3_init,
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.is_default = 1,
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};
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static void puv3_machine_init(void)
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{
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qemu_register_machine(&puv3_machine);
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}
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machine_init(puv3_machine_init)
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