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332dab6878
This patch adds the support of the '-cpu rv128' option to qemu-system-riscv64 so that we can indicate that we want to run rv128 executables. Still, there is no support for 128-bit insns at that stage so qemu fails miserably (as expected) if launched with this option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr [ Changed by AF - Rename CPU to "x-rv128" ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
402 lines
12 KiB
C
402 lines
12 KiB
C
/*
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* RISC-V GDB Server Stub
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "exec/gdbstub.h"
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#include "cpu.h"
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struct TypeSize {
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const char *gdb_type;
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const char *id;
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int size;
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const char suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", "quads", 128, 'q' },
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/* 64 bit */
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{ "uint64", "longs", 64, 'l' },
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/* 32 bit */
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{ "uint32", "words", 32, 'w' },
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/* 16 bit */
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{ "uint16", "shorts", 16, 's' },
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/*
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* TODO: currently there is no reliable way of telling
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* if the remote gdb actually understands ieee_half so
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* we don't expose it in the target description for now.
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* { "ieee_half", 16, 'h', 'f' },
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*/
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/* bytes */
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{ "uint8", "bytes", 8, 'b' },
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};
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int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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}
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return 0;
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}
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int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n == 0) {
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/* discard writes to x0 */
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return sizeof(target_ulong);
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} else if (n < 32) {
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env->gpr[n] = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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} else if (n == 32) {
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env->pc = ldtul_p(mem_buf);
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
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{
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if (n < 32) {
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if (env->misa_ext & RVD) {
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return gdb_get_reg64(buf, env->fpr[n]);
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}
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if (env->misa_ext & RVF) {
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return gdb_get_reg32(buf, env->fpr[n]);
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}
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = 0;
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int result;
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/*
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* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 32, &val,
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0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < 32) {
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env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
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return sizeof(uint64_t);
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/* there is hole between ft11 and fflags in fpu.xml */
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} else if (n < 36 && n > 32) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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/*
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* CSR_FFLAGS is at index 1 in csr_register, and gdb says it is FP
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* register 33, so we recalculate the map index.
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* This also works for CSR_FRM and CSR_FCSR.
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*/
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result = riscv_csrrw_debug(env, n - 32, NULL,
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val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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/*
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* Convert register index number passed by GDB to the correspond
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* vector CSR number. Vector CSRs are defined after vector registers
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* in dynamic generated riscv-vector.xml, thus the starting register index
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* of vector CSRs is 32.
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* Return 0 if register index number is out of range.
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*/
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static int riscv_gdb_vector_csrno(int num_regs)
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{
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/*
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* The order of vector CSRs in the switch case
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* should match with the order defined in csr_ops[].
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*/
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switch (num_regs) {
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case 32:
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return CSR_VSTART;
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case 33:
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return CSR_VXSAT;
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case 34:
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return CSR_VXRM;
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case 35:
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return CSR_VCSR;
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case 36:
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return CSR_VL;
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case 37:
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return CSR_VTYPE;
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case 38:
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return CSR_VLENB;
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default:
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/* Unknown register. */
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return 0;
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}
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}
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static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
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{
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uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
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if (n < 32) {
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int i;
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int cnt = 0;
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for (i = 0; i < vlenb; i += 8) {
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cnt += gdb_get_reg64(buf,
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env->vreg[(n * vlenb + i) / 8]);
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}
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return cnt;
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}
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int csrno = riscv_gdb_vector_csrno(n);
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if (!csrno) {
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return 0;
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}
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target_ulong val = 0;
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int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
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if (result == 0) {
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return gdb_get_regl(buf, val);
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}
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return 0;
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}
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static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
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if (n < 32) {
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int i;
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for (i = 0; i < vlenb; i += 8) {
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env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
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}
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return vlenb;
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}
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int csrno = riscv_gdb_vector_csrno(n);
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if (!csrno) {
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return 0;
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}
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target_ulong val = ldtul_p(mem_buf);
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int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
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if (result == 0) {
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)
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{
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = 0;
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int result;
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result = riscv_csrrw_debug(env, n, &val, 0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)
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{
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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result = riscv_csrrw_debug(env, n, NULL, val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
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{
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if (n == 0) {
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#ifdef CONFIG_USER_ONLY
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return gdb_get_regl(buf, 0);
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#else
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return gdb_get_regl(buf, cs->priv);
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#endif
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}
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return 0;
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}
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static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
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{
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if (n == 0) {
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#ifndef CONFIG_USER_ONLY
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cs->priv = ldtul_p(mem_buf) & 0x3;
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if (cs->priv == PRV_H) {
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cs->priv = PRV_S;
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}
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#endif
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return sizeof(target_ulong);
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}
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return 0;
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}
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static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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GString *s = g_string_new(NULL);
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riscv_csr_predicate_fn predicate;
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int bitsize = 16 << env->misa_mxl_max;
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int i;
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/* Until gdb knows about 128-bit registers */
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if (bitsize > 64) {
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bitsize = 64;
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}
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.csr\">");
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for (i = 0; i < CSR_TABLE_SIZE; i++) {
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predicate = csr_ops[i].predicate;
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if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
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if (csr_ops[i].name) {
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g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
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} else {
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g_string_append_printf(s, "<reg name=\"csr%03x\"", i);
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}
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g_string_append_printf(s, " bitsize=\"%d\"", bitsize);
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g_string_append_printf(s, " regnum=\"%d\"/>", base_reg + i);
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}
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}
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g_string_append_printf(s, "</feature>");
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cpu->dyn_csr_xml = g_string_free(s, false);
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return CSR_TABLE_SIZE;
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}
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static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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GString *s = g_string_new(NULL);
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g_autoptr(GString) ts = g_string_new("");
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int reg_width = cpu->cfg.vlen;
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int num_regs = 0;
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int i;
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g_string_printf(s, "<?xml version=\"1.0\"?>");
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g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
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g_string_append_printf(s, "<feature name=\"org.gnu.gdb.riscv.vector\">");
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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g_string_printf(ts, "%s", vec_lanes[i].id);
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g_string_append_printf(s,
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"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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ts->str, vec_lanes[i].gdb_type, count);
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}
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/* Define unions */
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g_string_append_printf(s, "<union id=\"riscv_vector\">");
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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g_string_append_printf(s, "<field name=\"%c\" type=\"%s\"/>",
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vec_lanes[i].suffix,
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vec_lanes[i].id);
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}
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g_string_append(s, "</union>");
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/* Define vector registers */
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for (i = 0; i < 32; i++) {
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g_string_append_printf(s,
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"<reg name=\"v%d\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"riscv_vector\"/>",
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i, reg_width, base_reg++);
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num_regs++;
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}
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/* Define vector CSRs */
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const char *vector_csrs[7] = {
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"vstart", "vxsat", "vxrm", "vcsr",
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"vl", "vtype", "vlenb"
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};
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for (i = 0; i < 7; i++) {
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g_string_append_printf(s,
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"<reg name=\"%s\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"int\"/>",
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vector_csrs[i], TARGET_LONG_BITS, base_reg++);
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num_regs++;
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}
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g_string_append_printf(s, "</feature>");
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cpu->dyn_vreg_xml = g_string_free(s, false);
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return num_regs;
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}
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (env->misa_ext & RVD) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-64bit-fpu.xml", 0);
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} else if (env->misa_ext & RVF) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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36, "riscv-32bit-fpu.xml", 0);
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}
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if (env->misa_ext & RVV) {
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gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
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ricsv_gen_dynamic_vector_xml(cs,
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cs->gdb_num_regs),
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"riscv-vector.xml", 0);
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}
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#if defined(TARGET_RISCV32)
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
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1, "riscv-32bit-virtual.xml", 0);
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#elif defined(TARGET_RISCV64)
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
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1, "riscv-64bit-virtual.xml", 0);
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#endif
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gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
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riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
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"riscv-csr.xml", 0);
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}
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