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709044fd2d
The PNV_XSCOM_BASE and PNV_XSCOM_SIZE macros are specific to POWER8 and they are used when the device tree is populated and the MMIO region created, even for POWER9 chips. This is not too much of a problem today because we don't have important devices on the second chip, but we might have oneday (PHBs). Fix by using the appropriate macros in case of P9. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190612174345.9799-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/*
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* QEMU PowerPC PowerNV XSCOM bus definitions
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_XSCOM_H
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#define PPC_PNV_XSCOM_H
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#include "qom/object.h"
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typedef struct PnvXScomInterface {
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Object parent;
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} PnvXScomInterface;
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#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
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#define PNV_XSCOM_INTERFACE(obj) \
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OBJECT_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
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#define PNV_XSCOM_INTERFACE_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvXScomInterfaceClass, (klass), \
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TYPE_PNV_XSCOM_INTERFACE)
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#define PNV_XSCOM_INTERFACE_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvXScomInterfaceClass, (obj), TYPE_PNV_XSCOM_INTERFACE)
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typedef struct PnvXScomInterfaceClass {
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InterfaceClass parent;
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int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
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} PnvXScomInterfaceClass;
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/*
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* Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
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*
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* GPIO 0x1100xxxx
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* SCOM 0x1101xxxx
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* OHA 0x1102xxxx
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* CLOCK CTL 0x1103xxxx
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* FIR 0x1104xxxx
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* THERM 0x1105xxxx
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* <reserved> 0x1106xxxx
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* ..
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* 0x110Exxxx
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* PCB SLAVE 0x110Fxxxx
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*/
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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#define PNV_XSCOM_PSIHB_BASE 0x2010900
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#define PNV_XSCOM_PSIHB_SIZE 0x20
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV9_XSCOM_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV9_XSCOM_EC_SIZE 0x100000
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#define PNV9_XSCOM_EQ_BASE(core) \
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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#define PNV9_XSCOM_PSIHB_BASE 0x5012900
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#define PNV9_XSCOM_PSIHB_SIZE 0x100
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#define PNV9_XSCOM_XIVE_BASE 0x5013000
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#define PNV9_XSCOM_XIVE_SIZE 0x300
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extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
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extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset);
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extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
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MemoryRegion *mr);
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extern void pnv_xscom_region_init(MemoryRegion *mr,
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struct Object *owner,
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const MemoryRegionOps *ops,
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void *opaque,
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const char *name,
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uint64_t size);
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#endif /* PPC_PNV_XSCOM_H */
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