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7ddd4ceaac
We don't need to explicit this obvious switch fall through. Stay consistent with the rest of the codebase. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191218192526.13845-7-philmd@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
757 lines
25 KiB
C
757 lines
25 KiB
C
/*
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* Copyright (c) 2018, Impinj, Inc.
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*
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* Designware PCIe IP block emulation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/pci-host/designware.h"
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#define DESIGNWARE_PCIE_PORT_LINK_CONTROL 0x710
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#define DESIGNWARE_PCIE_PHY_DEBUG_R1 0x72C
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#define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4)
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#define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE BIT(17)
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#define DESIGNWARE_PCIE_MSI_ADDR_LO 0x820
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#define DESIGNWARE_PCIE_MSI_ADDR_HI 0x824
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#define DESIGNWARE_PCIE_MSI_INTR0_ENABLE 0x828
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#define DESIGNWARE_PCIE_MSI_INTR0_MASK 0x82C
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#define DESIGNWARE_PCIE_MSI_INTR0_STATUS 0x830
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#define DESIGNWARE_PCIE_ATU_VIEWPORT 0x900
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#define DESIGNWARE_PCIE_ATU_REGION_INBOUND BIT(31)
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#define DESIGNWARE_PCIE_ATU_CR1 0x904
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#define DESIGNWARE_PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define DESIGNWARE_PCIE_ATU_CR2 0x908
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#define DESIGNWARE_PCIE_ATU_ENABLE BIT(31)
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#define DESIGNWARE_PCIE_ATU_LOWER_BASE 0x90C
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#define DESIGNWARE_PCIE_ATU_UPPER_BASE 0x910
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#define DESIGNWARE_PCIE_ATU_LIMIT 0x914
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#define DESIGNWARE_PCIE_ATU_LOWER_TARGET 0x918
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#define DESIGNWARE_PCIE_ATU_BUS(x) (((x) >> 24) & 0xff)
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#define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff)
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#define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C
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#define DESIGNWARE_PCIE_IRQ_MSI 3
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static DesignwarePCIEHost *
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designware_pcie_root_to_host(DesignwarePCIERoot *root)
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{
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BusState *bus = qdev_get_parent_bus(DEVICE(root));
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return DESIGNWARE_PCIE_HOST(bus->parent);
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}
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static void designware_pcie_root_msi_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque);
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DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
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root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable;
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if (root->msi.intr[0].status & ~root->msi.intr[0].mask) {
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qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1);
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}
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}
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static const MemoryRegionOps designware_pci_host_msi_ops = {
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.write = designware_pcie_root_msi_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root)
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{
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MemoryRegion *mem = &root->msi.iomem;
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const uint64_t base = root->msi.base;
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const bool enable = root->msi.intr[0].enable;
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memory_region_set_address(mem, base);
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memory_region_set_enabled(mem, enable);
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}
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static DesignwarePCIEViewport *
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designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root)
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{
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const unsigned int idx = root->atu_viewport & 0xF;
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const unsigned int dir =
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!!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND);
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return &root->viewports[dir][idx];
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}
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static uint32_t
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designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len)
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{
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DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
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DesignwarePCIEViewport *viewport =
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designware_pcie_root_get_current_viewport(root);
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uint32_t val;
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switch (address) {
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case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
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/*
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* Linux guest uses this register only to configure number of
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* PCIE lane (which in our case is irrelevant) and doesn't
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* really care about the value it reads from this register
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*/
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val = 0xDEADBEEF;
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break;
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case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
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/*
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* To make sure that any code in guest waiting for speed
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* change does not time out we always report
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* PORT_LOGIC_SPEED_CHANGE as set
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*/
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val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE;
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break;
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case DESIGNWARE_PCIE_MSI_ADDR_LO:
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val = root->msi.base;
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break;
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case DESIGNWARE_PCIE_MSI_ADDR_HI:
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val = root->msi.base >> 32;
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
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val = root->msi.intr[0].enable;
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_MASK:
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val = root->msi.intr[0].mask;
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
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val = root->msi.intr[0].status;
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break;
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case DESIGNWARE_PCIE_PHY_DEBUG_R1:
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val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
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break;
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case DESIGNWARE_PCIE_ATU_VIEWPORT:
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val = root->atu_viewport;
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break;
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case DESIGNWARE_PCIE_ATU_LOWER_BASE:
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val = viewport->base;
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break;
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case DESIGNWARE_PCIE_ATU_UPPER_BASE:
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val = viewport->base >> 32;
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break;
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case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
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val = viewport->target;
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break;
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case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
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val = viewport->target >> 32;
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break;
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case DESIGNWARE_PCIE_ATU_LIMIT:
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val = viewport->limit;
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break;
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case DESIGNWARE_PCIE_ATU_CR1:
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case DESIGNWARE_PCIE_ATU_CR2:
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val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) /
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sizeof(uint32_t)];
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break;
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default:
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val = pci_default_read_config(d, address, len);
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break;
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}
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return val;
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}
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static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr,
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uint64_t *val, unsigned len)
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{
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DesignwarePCIEViewport *viewport = opaque;
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DesignwarePCIERoot *root = viewport->root;
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const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target);
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const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target);
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PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root));
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PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn);
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if (pcidev) {
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addr &= pci_config_size(pcidev) - 1;
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if (val) {
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pci_host_config_write_common(pcidev, addr,
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pci_config_size(pcidev),
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*val, len);
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} else {
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return pci_host_config_read_common(pcidev, addr,
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pci_config_size(pcidev),
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len);
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}
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}
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return UINT64_MAX;
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}
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static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr,
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unsigned len)
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{
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return designware_pcie_root_data_access(opaque, addr, NULL, len);
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}
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static void designware_pcie_root_data_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned len)
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{
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designware_pcie_root_data_access(opaque, addr, &val, len);
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}
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static const MemoryRegionOps designware_pci_host_conf_ops = {
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.read = designware_pcie_root_data_read,
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.write = designware_pcie_root_data_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
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DesignwarePCIEViewport *viewport)
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{
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const uint64_t target = viewport->target;
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const uint64_t base = viewport->base;
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const uint64_t size = (uint64_t)viewport->limit - base + 1;
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const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
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MemoryRegion *current, *other;
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if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
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current = &viewport->mem;
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other = &viewport->cfg;
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memory_region_set_alias_offset(current, target);
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} else {
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current = &viewport->cfg;
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other = &viewport->mem;
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}
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/*
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* An outbound viewport can be reconfigure from being MEM to CFG,
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* to account for that we disable the "other" memory region that
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* becomes unused due to that fact.
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*/
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memory_region_set_enabled(other, false);
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if (enabled) {
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memory_region_set_size(current, size);
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memory_region_set_address(current, base);
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}
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memory_region_set_enabled(current, enabled);
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}
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static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d);
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DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
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DesignwarePCIEViewport *viewport =
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designware_pcie_root_get_current_viewport(root);
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switch (address) {
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case DESIGNWARE_PCIE_PORT_LINK_CONTROL:
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case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL:
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case DESIGNWARE_PCIE_PHY_DEBUG_R1:
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/* No-op */
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break;
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case DESIGNWARE_PCIE_MSI_ADDR_LO:
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root->msi.base &= 0xFFFFFFFF00000000ULL;
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root->msi.base |= val;
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designware_pcie_root_update_msi_mapping(root);
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break;
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case DESIGNWARE_PCIE_MSI_ADDR_HI:
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root->msi.base &= 0x00000000FFFFFFFFULL;
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root->msi.base |= (uint64_t)val << 32;
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designware_pcie_root_update_msi_mapping(root);
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
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root->msi.intr[0].enable = val;
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designware_pcie_root_update_msi_mapping(root);
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_MASK:
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root->msi.intr[0].mask = val;
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break;
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case DESIGNWARE_PCIE_MSI_INTR0_STATUS:
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root->msi.intr[0].status ^= val;
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if (!root->msi.intr[0].status) {
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qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0);
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}
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break;
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case DESIGNWARE_PCIE_ATU_VIEWPORT:
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root->atu_viewport = val;
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break;
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case DESIGNWARE_PCIE_ATU_LOWER_BASE:
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viewport->base &= 0xFFFFFFFF00000000ULL;
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viewport->base |= val;
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break;
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case DESIGNWARE_PCIE_ATU_UPPER_BASE:
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viewport->base &= 0x00000000FFFFFFFFULL;
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viewport->base |= (uint64_t)val << 32;
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break;
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case DESIGNWARE_PCIE_ATU_LOWER_TARGET:
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viewport->target &= 0xFFFFFFFF00000000ULL;
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viewport->target |= val;
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break;
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case DESIGNWARE_PCIE_ATU_UPPER_TARGET:
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viewport->target &= 0x00000000FFFFFFFFULL;
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viewport->target |= val;
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break;
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case DESIGNWARE_PCIE_ATU_LIMIT:
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viewport->limit = val;
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break;
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case DESIGNWARE_PCIE_ATU_CR1:
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viewport->cr[0] = val;
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break;
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case DESIGNWARE_PCIE_ATU_CR2:
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viewport->cr[1] = val;
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designware_pcie_update_viewport(root, viewport);
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break;
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default:
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pci_bridge_write_config(d, address, val, len);
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break;
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}
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}
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static char *designware_pcie_viewport_name(const char *direction,
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unsigned int i,
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const char *type)
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{
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return g_strdup_printf("PCI %s Viewport %u [%s]",
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direction, i, type);
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}
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static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
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{
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DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev);
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DesignwarePCIEHost *host = designware_pcie_root_to_host(root);
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MemoryRegion *address_space = &host->pci.memory;
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PCIBridge *br = PCI_BRIDGE(dev);
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DesignwarePCIEViewport *viewport;
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/*
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* Dummy values used for initial configuration of MemoryRegions
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* that belong to a given viewport
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*/
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const hwaddr dummy_offset = 0;
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const uint64_t dummy_size = 4;
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size_t i;
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br->bus_name = "dw-pcie";
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pci_set_word(dev->config + PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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pci_config_set_interrupt_pin(dev->config, 1);
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pci_bridge_initfn(dev, TYPE_PCIE_BUS);
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pcie_port_init_reg(dev);
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pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT,
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0, &error_fatal);
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msi_nonbroken = true;
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msi_init(dev, 0x50, 32, true, true, &error_fatal);
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for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) {
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MemoryRegion *source, *destination, *mem;
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const char *direction;
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char *name;
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viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i];
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viewport->inbound = true;
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viewport->base = 0x0000000000000000ULL;
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viewport->target = 0x0000000000000000ULL;
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viewport->limit = UINT32_MAX;
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viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
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source = &host->pci.address_space_root;
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destination = get_system_memory();
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direction = "Inbound";
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/*
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* Configure MemoryRegion implementing PCI -> CPU memory
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* access
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*/
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mem = &viewport->mem;
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name = designware_pcie_viewport_name(direction, i, "MEM");
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memory_region_init_alias(mem, OBJECT(root), name, destination,
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dummy_offset, dummy_size);
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memory_region_add_subregion_overlap(source, dummy_offset, mem, -1);
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memory_region_set_enabled(mem, false);
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g_free(name);
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viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i];
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viewport->root = root;
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viewport->inbound = false;
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viewport->base = 0x0000000000000000ULL;
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viewport->target = 0x0000000000000000ULL;
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viewport->limit = UINT32_MAX;
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viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM;
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destination = &host->pci.memory;
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direction = "Outbound";
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source = get_system_memory();
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/*
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* Configure MemoryRegion implementing CPU -> PCI memory
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* access
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*/
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mem = &viewport->mem;
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name = designware_pcie_viewport_name(direction, i, "MEM");
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memory_region_init_alias(mem, OBJECT(root), name, destination,
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dummy_offset, dummy_size);
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memory_region_add_subregion(source, dummy_offset, mem);
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memory_region_set_enabled(mem, false);
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g_free(name);
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/*
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* Configure MemoryRegion implementing access to configuration
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* space
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*/
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mem = &viewport->cfg;
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name = designware_pcie_viewport_name(direction, i, "CFG");
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memory_region_init_io(&viewport->cfg, OBJECT(root),
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&designware_pci_host_conf_ops,
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viewport, name, dummy_size);
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memory_region_add_subregion(source, dummy_offset, mem);
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memory_region_set_enabled(mem, false);
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g_free(name);
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}
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/*
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* If no inbound iATU windows are configured, HW defaults to
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* letting inbound TLPs to pass in. We emulate that by exlicitly
|
|
* configuring first inbound window to cover all of target's
|
|
* address space.
|
|
*
|
|
* NOTE: This will not work correctly for the case when first
|
|
* configured inbound window is window 0
|
|
*/
|
|
viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0];
|
|
viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE;
|
|
designware_pcie_update_viewport(root, viewport);
|
|
|
|
memory_region_init_io(&root->msi.iomem, OBJECT(root),
|
|
&designware_pci_host_msi_ops,
|
|
root, "pcie-msi", 0x4);
|
|
/*
|
|
* We initially place MSI interrupt I/O region a adress 0 and
|
|
* disable it. It'll be later moved to correct offset and enabled
|
|
* in designware_pcie_root_update_msi_mapping() as a part of
|
|
* initialization done by guest OS
|
|
*/
|
|
memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem);
|
|
memory_region_set_enabled(&root->msi.iomem, false);
|
|
}
|
|
|
|
static void designware_pcie_set_irq(void *opaque, int irq_num, int level)
|
|
{
|
|
DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque);
|
|
|
|
qemu_set_irq(host->pci.irqs[irq_num], level);
|
|
}
|
|
|
|
static const char *
|
|
designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus)
|
|
{
|
|
return "0000:00";
|
|
}
|
|
|
|
static const VMStateDescription vmstate_designware_pcie_msi_bank = {
|
|
.name = "designware-pcie-msi-bank",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(enable, DesignwarePCIEMSIBank),
|
|
VMSTATE_UINT32(mask, DesignwarePCIEMSIBank),
|
|
VMSTATE_UINT32(status, DesignwarePCIEMSIBank),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_designware_pcie_msi = {
|
|
.name = "designware-pcie-msi",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(base, DesignwarePCIEMSI),
|
|
VMSTATE_STRUCT_ARRAY(intr,
|
|
DesignwarePCIEMSI,
|
|
DESIGNWARE_PCIE_NUM_MSI_BANKS,
|
|
1,
|
|
vmstate_designware_pcie_msi_bank,
|
|
DesignwarePCIEMSIBank),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_designware_pcie_viewport = {
|
|
.name = "designware-pcie-viewport",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT64(base, DesignwarePCIEViewport),
|
|
VMSTATE_UINT64(target, DesignwarePCIEViewport),
|
|
VMSTATE_UINT32(limit, DesignwarePCIEViewport),
|
|
VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_designware_pcie_root = {
|
|
.name = "designware-pcie-root",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
|
|
VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot),
|
|
VMSTATE_STRUCT_2DARRAY(viewports,
|
|
DesignwarePCIERoot,
|
|
2,
|
|
DESIGNWARE_PCIE_NUM_VIEWPORTS,
|
|
1,
|
|
vmstate_designware_pcie_viewport,
|
|
DesignwarePCIEViewport),
|
|
VMSTATE_STRUCT(msi,
|
|
DesignwarePCIERoot,
|
|
1,
|
|
vmstate_designware_pcie_msi,
|
|
DesignwarePCIEMSI),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void designware_pcie_root_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_SYNOPSYS;
|
|
k->device_id = 0xABCD;
|
|
k->revision = 0;
|
|
k->class_id = PCI_CLASS_BRIDGE_PCI;
|
|
k->is_bridge = true;
|
|
k->exit = pci_bridge_exitfn;
|
|
k->realize = designware_pcie_root_realize;
|
|
k->config_read = designware_pcie_root_config_read;
|
|
k->config_write = designware_pcie_root_config_write;
|
|
|
|
dc->reset = pci_bridge_reset;
|
|
/*
|
|
* PCI-facing part of the host bridge, not usable without the
|
|
* host-facing part, which can't be device_add'ed, yet.
|
|
*/
|
|
dc->user_creatable = false;
|
|
dc->vmsd = &vmstate_designware_pcie_root;
|
|
}
|
|
|
|
static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr,
|
|
unsigned int size)
|
|
{
|
|
PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
|
|
PCIDevice *device = pci_find_device(pci->bus, 0, 0);
|
|
|
|
return pci_host_config_read_common(device,
|
|
addr,
|
|
pci_config_size(device),
|
|
size);
|
|
}
|
|
|
|
static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned int size)
|
|
{
|
|
PCIHostState *pci = PCI_HOST_BRIDGE(opaque);
|
|
PCIDevice *device = pci_find_device(pci->bus, 0, 0);
|
|
|
|
return pci_host_config_write_common(device,
|
|
addr,
|
|
pci_config_size(device),
|
|
val, size);
|
|
}
|
|
|
|
static const MemoryRegionOps designware_pci_mmio_ops = {
|
|
.read = designware_pcie_host_mmio_read,
|
|
.write = designware_pcie_host_mmio_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.impl = {
|
|
/*
|
|
* Our device would not work correctly if the guest was doing
|
|
* unaligned access. This might not be a limitation on the real
|
|
* device but in practice there is no reason for a guest to access
|
|
* this device unaligned.
|
|
*/
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
.unaligned = false,
|
|
},
|
|
};
|
|
|
|
static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque,
|
|
int devfn)
|
|
{
|
|
DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque);
|
|
|
|
return &s->pci.address_space;
|
|
}
|
|
|
|
static void designware_pcie_host_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
|
|
DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
size_t i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) {
|
|
sysbus_init_irq(sbd, &s->pci.irqs[i]);
|
|
}
|
|
|
|
memory_region_init_io(&s->mmio,
|
|
OBJECT(s),
|
|
&designware_pci_mmio_ops,
|
|
s,
|
|
"pcie.reg", 4 * 1024);
|
|
sysbus_init_mmio(sbd, &s->mmio);
|
|
|
|
memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16);
|
|
memory_region_init(&s->pci.memory, OBJECT(s),
|
|
"pcie-bus-memory",
|
|
UINT64_MAX);
|
|
|
|
pci->bus = pci_register_root_bus(dev, "pcie",
|
|
designware_pcie_set_irq,
|
|
pci_swizzle_map_irq_fn,
|
|
s,
|
|
&s->pci.memory,
|
|
&s->pci.io,
|
|
0, 4,
|
|
TYPE_PCIE_BUS);
|
|
|
|
memory_region_init(&s->pci.address_space_root,
|
|
OBJECT(s),
|
|
"pcie-bus-address-space-root",
|
|
UINT64_MAX);
|
|
memory_region_add_subregion(&s->pci.address_space_root,
|
|
0x0, &s->pci.memory);
|
|
address_space_init(&s->pci.address_space,
|
|
&s->pci.address_space_root,
|
|
"pcie-bus-address-space");
|
|
pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s);
|
|
|
|
qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus));
|
|
qdev_init_nofail(DEVICE(&s->root));
|
|
}
|
|
|
|
static const VMStateDescription vmstate_designware_pcie_host = {
|
|
.name = "designware-pcie-host",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(root,
|
|
DesignwarePCIEHost,
|
|
1,
|
|
vmstate_designware_pcie_root,
|
|
DesignwarePCIERoot),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void designware_pcie_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
|
|
|
|
hc->root_bus_path = designware_pcie_host_root_bus_path;
|
|
dc->realize = designware_pcie_host_realize;
|
|
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
|
|
dc->fw_name = "pci";
|
|
dc->vmsd = &vmstate_designware_pcie_host;
|
|
}
|
|
|
|
static void designware_pcie_host_init(Object *obj)
|
|
{
|
|
DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj);
|
|
DesignwarePCIERoot *root = &s->root;
|
|
|
|
object_initialize_child(obj, "root", root, sizeof(*root),
|
|
TYPE_DESIGNWARE_PCIE_ROOT, &error_abort, NULL);
|
|
qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
|
|
qdev_prop_set_bit(DEVICE(root), "multifunction", false);
|
|
}
|
|
|
|
static const TypeInfo designware_pcie_root_info = {
|
|
.name = TYPE_DESIGNWARE_PCIE_ROOT,
|
|
.parent = TYPE_PCI_BRIDGE,
|
|
.instance_size = sizeof(DesignwarePCIERoot),
|
|
.class_init = designware_pcie_root_class_init,
|
|
.interfaces = (InterfaceInfo[]) {
|
|
{ INTERFACE_PCIE_DEVICE },
|
|
{ }
|
|
},
|
|
};
|
|
|
|
static const TypeInfo designware_pcie_host_info = {
|
|
.name = TYPE_DESIGNWARE_PCIE_HOST,
|
|
.parent = TYPE_PCI_HOST_BRIDGE,
|
|
.instance_size = sizeof(DesignwarePCIEHost),
|
|
.instance_init = designware_pcie_host_init,
|
|
.class_init = designware_pcie_host_class_init,
|
|
};
|
|
|
|
static void designware_pcie_register(void)
|
|
{
|
|
type_register_static(&designware_pcie_root_info);
|
|
type_register_static(&designware_pcie_host_info);
|
|
}
|
|
type_init(designware_pcie_register)
|