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09e24b10de
Fix:
hw/nios2/10m50_devboard.c: In function ‘nios2_10m50_ghrd_init’:
hw/nios2/10m50_devboard.c:101:22: warning: declaration of ‘dev’ shadows a previous local [-Wshadow=compatible-local]
101 | DeviceState *dev = qdev_new(TYPE_NIOS2_VIC);
| ^~~
hw/nios2/10m50_devboard.c:60:18: note: shadowed declaration is here
60 | DeviceState *dev;
| ^~~
hw/nios2/10m50_devboard.c:110:18: warning: declaration of ‘i’ shadows a previous local [-Wshadow=compatible-local]
110 | for (int i = 0; i < 32; i++) {
| ^
hw/nios2/10m50_devboard.c:67:9: note: shadowed declaration is here
67 | int i;
| ^
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230904161235.84651-15-philmd@linaro.org>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
181 lines
6.1 KiB
C
181 lines
6.1 KiB
C
/*
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* Altera 10M50 Nios2 GHRD
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*
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* Copyright (c) 2016 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on LabX device code
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/intc/nios2_vic.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "qemu/config-file.h"
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#include "boot.h"
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struct Nios2MachineState {
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MachineState parent_obj;
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MemoryRegion phys_tcm;
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MemoryRegion phys_tcm_alias;
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MemoryRegion phys_ram;
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MemoryRegion phys_ram_alias;
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bool vic;
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};
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#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd")
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OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE)
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#define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb"
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static void nios2_10m50_ghrd_init(MachineState *machine)
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{
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Nios2MachineState *nms = NIOS2_MACHINE(machine);
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Nios2CPU *cpu;
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DeviceState *dev;
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MemoryRegion *address_space_mem = get_system_memory();
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ram_addr_t tcm_base = 0x0;
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ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
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ram_addr_t ram_base = 0x08000000;
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ram_addr_t ram_size = 0x08000000;
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qemu_irq irq[32];
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int i;
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/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
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memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size,
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&error_abort);
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memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias",
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&nms->phys_tcm, 0, tcm_size);
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memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tcm);
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memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
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&nms->phys_tcm_alias);
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/* Physical DRAM with alias at 0xc0000000 */
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memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size,
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&error_abort);
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memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias",
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&nms->phys_ram, 0, ram_size);
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memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ram);
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memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
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&nms->phys_ram_alias);
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/* Create CPU. We need to set eic_present between init and realize. */
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cpu = NIOS2_CPU(object_new(TYPE_NIOS2_CPU));
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/* Enable the External Interrupt Controller within the CPU. */
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cpu->eic_present = nms->vic;
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/* Configure new exception vectors. */
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cpu->reset_addr = 0xd4000000;
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cpu->exception_addr = 0xc8000120;
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cpu->fast_tlb_miss_addr = 0xc0000100;
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qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
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if (nms->vic) {
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dev = qdev_new(TYPE_NIOS2_VIC);
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MemoryRegion *dev_mr;
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qemu_irq cpu_irq;
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object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
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memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr);
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} else {
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i);
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}
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}
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/* Register: Altera 16550 UART */
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serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200,
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serial_hd(0), DEVICE_NATIVE_ENDIAN);
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/* Register: Timer sys_clk_timer */
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dev = qdev_new("ALTR.timer");
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qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xf8001440);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[0]);
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/* Register: Timer sys_clk_timer_1 */
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dev = qdev_new("ALTR.timer");
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qdev_prop_set_uint32(dev, "clock-frequency", 75 * 1000000);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]);
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nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
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BINARY_DEVICE_TREE_FILE, NULL);
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}
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static bool get_vic(Object *obj, Error **errp)
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{
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Nios2MachineState *nms = NIOS2_MACHINE(obj);
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return nms->vic;
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}
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static void set_vic(Object *obj, bool value, Error **errp)
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{
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Nios2MachineState *nms = NIOS2_MACHINE(obj);
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nms->vic = value;
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}
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static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "Altera 10M50 GHRD Nios II design";
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mc->init = nios2_10m50_ghrd_init;
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mc->is_default = true;
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object_class_property_add_bool(oc, "vic", get_vic, set_vic);
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object_class_property_set_description(oc, "vic",
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"Set on/off to enable/disable the Vectored Interrupt Controller");
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}
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static const TypeInfo nios2_10m50_ghrd_type_info = {
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.name = TYPE_NIOS2_MACHINE,
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.parent = TYPE_MACHINE,
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.instance_size = sizeof(Nios2MachineState),
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.class_init = nios2_10m50_ghrd_class_init,
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};
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static void nios2_10m50_ghrd_type_init(void)
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{
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type_register_static(&nios2_10m50_ghrd_type_info);
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}
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type_init(nios2_10m50_ghrd_type_init);
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