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22548760ca
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
484 lines
12 KiB
C
484 lines
12 KiB
C
/*
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* QEMU Sparc SLAVIO aux io port emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sun4m.h"
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#include "sysemu.h"
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/* debug misc */
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//#define DEBUG_MISC
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/*
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* This is the auxio port, chip control and system control part of
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* chip STP2001 (Slave I/O), also produced as NCR89C105. See
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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*
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* This also includes the PMC CPU idle controller.
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*/
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#ifdef DEBUG_MISC
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#define MISC_DPRINTF(fmt, args...) \
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do { printf("MISC: " fmt , ##args); } while (0)
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#else
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#define MISC_DPRINTF(fmt, args...)
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#endif
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typedef struct MiscState {
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qemu_irq irq;
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uint8_t config;
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uint8_t aux1, aux2;
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uint8_t diag, mctrl;
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uint32_t sysctrl;
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uint16_t leds;
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CPUState *env;
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qemu_irq fdc_tc;
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} MiscState;
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#define MISC_SIZE 1
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#define SYSCTRL_MAXADDR 3
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#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
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#define LED_MAXADDR 1
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#define LED_SIZE (LED_MAXADDR + 1)
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#define MISC_MASK 0x0fff0000
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#define MISC_LEDS 0x01600000
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#define MISC_CFG 0x01800000
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#define MISC_DIAG 0x01a00000
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#define MISC_MDM 0x01b00000
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#define MISC_SYS 0x01f00000
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#define AUX1_TC 0x02
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#define AUX2_PWROFF 0x01
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#define AUX2_PWRINTCLR 0x02
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#define AUX2_PWRFAIL 0x20
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#define CFG_PWRINTEN 0x08
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#define SYS_RESET 0x01
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#define SYS_RESETSTAT 0x02
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static void slavio_misc_update_irq(void *opaque)
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{
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MiscState *s = opaque;
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if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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MISC_DPRINTF("Raise IRQ\n");
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qemu_irq_raise(s->irq);
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} else {
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MISC_DPRINTF("Lower IRQ\n");
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qemu_irq_lower(s->irq);
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}
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}
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static void slavio_misc_reset(void *opaque)
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{
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MiscState *s = opaque;
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// Diagnostic and system control registers not cleared in reset
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s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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}
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void slavio_set_power_fail(void *opaque, int power_failing)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
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if (power_failing && (s->config & CFG_PWRINTEN)) {
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s->aux2 |= AUX2_PWRFAIL;
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} else {
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s->aux2 &= ~AUX2_PWRFAIL;
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}
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slavio_misc_update_irq(s);
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}
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static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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switch (addr & MISC_MASK) {
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case MISC_CFG:
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MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
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s->config = val & 0xff;
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slavio_misc_update_irq(s);
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break;
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case MISC_DIAG:
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MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
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s->diag = val & 0xff;
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break;
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case MISC_MDM:
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MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
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s->mctrl = val & 0xff;
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break;
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default:
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break;
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}
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}
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static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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switch (addr & MISC_MASK) {
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case MISC_CFG:
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ret = s->config;
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MISC_DPRINTF("Read config %2.2x\n", ret);
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break;
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case MISC_DIAG:
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ret = s->diag;
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MISC_DPRINTF("Read diag %2.2x\n", ret);
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break;
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case MISC_MDM:
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ret = s->mctrl;
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MISC_DPRINTF("Read modem control %2.2x\n", ret);
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break;
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default:
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break;
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}
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return ret;
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}
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static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
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slavio_misc_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
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slavio_misc_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
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if (val & AUX1_TC) {
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// Send a pulse to floppy terminal count line
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if (s->fdc_tc) {
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qemu_irq_raise(s->fdc_tc);
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qemu_irq_lower(s->fdc_tc);
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}
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val &= ~AUX1_TC;
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}
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s->aux1 = val & 0xff;
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}
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static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux1;
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MISC_DPRINTF("Read aux1 %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
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slavio_aux1_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
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slavio_aux1_mem_writeb,
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NULL,
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NULL,
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};
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static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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MISC_DPRINTF("Write aux2 %2.2x\n", val);
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val |= s->aux2 & AUX2_PWRFAIL;
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if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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val &= AUX2_PWROFF;
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s->aux2 = val;
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if (val & AUX2_PWROFF)
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qemu_system_shutdown_request();
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slavio_misc_update_irq(s);
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}
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static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0;
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ret = s->aux2;
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MISC_DPRINTF("Read aux2 %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
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slavio_aux2_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
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slavio_aux2_mem_writeb,
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NULL,
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NULL,
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};
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static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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MiscState *s = opaque;
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MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
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cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
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}
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static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = 0;
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MISC_DPRINTF("Read power management %2.2x\n", ret);
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return ret;
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}
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static CPUReadMemoryFunc *apc_mem_read[3] = {
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apc_mem_readb,
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NULL,
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NULL,
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};
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static CPUWriteMemoryFunc *apc_mem_write[3] = {
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apc_mem_writeb,
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NULL,
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NULL,
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};
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static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0, saddr;
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saddr = addr & SYSCTRL_MAXADDR;
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switch (saddr) {
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case 0:
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ret = s->sysctrl;
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break;
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default:
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break;
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}
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MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
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ret);
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return ret;
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}
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static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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uint32_t saddr;
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saddr = addr & SYSCTRL_MAXADDR;
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MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
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val);
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switch (saddr) {
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case 0:
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if (val & SYS_RESET) {
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s->sysctrl = SYS_RESETSTAT;
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qemu_system_reset_request();
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}
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
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NULL,
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NULL,
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slavio_sysctrl_mem_readl,
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};
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static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
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NULL,
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NULL,
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slavio_sysctrl_mem_writel,
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};
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static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
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{
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MiscState *s = opaque;
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uint32_t ret = 0, saddr;
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saddr = addr & LED_MAXADDR;
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switch (saddr) {
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case 0:
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ret = s->leds;
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break;
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default:
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break;
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}
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MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
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ret);
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return ret;
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}
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static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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MiscState *s = opaque;
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uint32_t saddr;
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saddr = addr & LED_MAXADDR;
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MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
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val);
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switch (saddr) {
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case 0:
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s->leds = val;
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break;
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default:
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break;
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}
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}
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static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
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NULL,
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slavio_led_mem_readw,
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NULL,
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};
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static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
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NULL,
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slavio_led_mem_writew,
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NULL,
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};
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static void slavio_misc_save(QEMUFile *f, void *opaque)
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{
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MiscState *s = opaque;
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uint32_t tmp = 0;
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uint8_t tmp8;
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qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
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qemu_put_8s(f, &s->config);
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qemu_put_8s(f, &s->aux1);
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qemu_put_8s(f, &s->aux2);
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qemu_put_8s(f, &s->diag);
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qemu_put_8s(f, &s->mctrl);
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tmp8 = s->sysctrl & 0xff;
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qemu_put_8s(f, &tmp8);
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}
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static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
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{
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MiscState *s = opaque;
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uint32_t tmp;
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uint8_t tmp8;
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if (version_id != 1)
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return -EINVAL;
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qemu_get_be32s(f, &tmp);
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qemu_get_8s(f, &s->config);
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qemu_get_8s(f, &s->aux1);
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qemu_get_8s(f, &s->aux2);
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qemu_get_8s(f, &s->diag);
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qemu_get_8s(f, &s->mctrl);
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qemu_get_8s(f, &tmp8);
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s->sysctrl = (uint32_t)tmp8;
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return 0;
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}
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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CPUState *env, qemu_irq **fdc_tc)
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{
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int io;
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MiscState *s;
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s = qemu_mallocz(sizeof(MiscState));
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if (!s)
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return NULL;
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if (base) {
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/* 8 bit registers */
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io = cpu_register_io_memory(0, slavio_misc_mem_read,
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slavio_misc_mem_write, s);
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// Slavio control
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cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
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// Diagnostics
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cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
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// Modem control
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cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
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/* 16 bit registers */
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io = cpu_register_io_memory(0, slavio_led_mem_read,
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slavio_led_mem_write, s);
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/* ss600mp diag LEDs */
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cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
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/* 32 bit registers */
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io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
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slavio_sysctrl_mem_write, s);
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// System control
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cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
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}
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// AUX 1 (Misc System Functions)
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if (aux1_base) {
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io = cpu_register_io_memory(0, slavio_aux1_mem_read,
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slavio_aux1_mem_write, s);
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cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
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}
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// AUX 2 (Software Powerdown Control)
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if (aux2_base) {
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io = cpu_register_io_memory(0, slavio_aux2_mem_read,
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slavio_aux2_mem_write, s);
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cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
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}
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// Power management (APC) XXX: not a Slavio device
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if (power_base) {
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io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
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cpu_register_physical_memory(power_base, MISC_SIZE, io);
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}
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s->irq = irq;
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s->env = env;
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*fdc_tc = &s->fdc_tc;
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register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
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s);
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qemu_register_reset(slavio_misc_reset, s);
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slavio_misc_reset(s);
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return s;
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}
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