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qemu/target-tilegx
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Richard Henderson 461aa6783e target-tilegx: Handle v1shl, v1shru, v1shrs 
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15 07:45:34 -07:00
..
cpu.c target-tilegx: Generate SEGV properly 2015-09-15 07:45:28 -07:00
cpu.h target-tilegx: Handle atomic instructions 2015-09-15 07:45:34 -07:00
helper.c target-tilegx: Handle most bit manipulation instructions 2015-09-15 07:45:33 -07:00
helper.h target-tilegx: Handle v1shl, v1shru, v1shrs 2015-09-15 07:45:34 -07:00
Makefile.objs target-tilegx: Handle v1shl, v1shru, v1shrs 2015-09-15 07:45:34 -07:00
opcode_tilegx.h target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1 2015-09-15 07:41:35 -07:00
simd_helper.c target-tilegx: Handle v1shl, v1shru, v1shrs 2015-09-15 07:45:34 -07:00
spr_def_64.h target-tilegx: Add special register information from Tilera Corporation 2015-09-15 07:41:35 -07:00
translate.c target-tilegx: Handle v1shl, v1shru, v1shrs 2015-09-15 07:45:34 -07:00