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ebc1fbb4a1
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
68 lines
2.0 KiB
C
68 lines
2.0 KiB
C
/*
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* Microsemi Smartfusion2 SoC
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*
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* Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_ARM_MSF2_SOC_H
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#define HW_ARM_MSF2_SOC_H
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#include "hw/arm/armv7m.h"
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#include "hw/timer/mss-timer.h"
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#include "hw/misc/msf2-sysreg.h"
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#include "hw/ssi/mss-spi.h"
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#define TYPE_MSF2_SOC "msf2-soc"
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#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
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#define MSF2_NUM_SPIS 2
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#define MSF2_NUM_UARTS 2
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/*
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* System timer consists of two programmable 32-bit
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* decrementing counters that generate individual interrupts to
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* the Cortex-M3 processor
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*/
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#define MSF2_NUM_TIMERS 2
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typedef struct MSF2State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMv7MState armv7m;
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char *cpu_type;
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char *part_name;
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uint64_t envm_size;
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uint64_t esram_size;
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uint32_t m3clk;
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uint8_t apb0div;
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uint8_t apb1div;
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MSF2SysregState sysreg;
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MSSTimerState timer;
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MSSSpiState spi[MSF2_NUM_SPIS];
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} MSF2State;
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#endif
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