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3b4fff1bd5
Convert the sparc CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-18-peter.maydell@linaro.org
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* QEMU SPARC CPU
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#ifndef QEMU_SPARC_CPU_QOM_H
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#define QEMU_SPARC_CPU_QOM_H
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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#ifdef TARGET_SPARC64
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#define TYPE_SPARC_CPU "sparc64-cpu"
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#else
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#define TYPE_SPARC_CPU "sparc-cpu"
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#endif
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OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
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typedef struct sparc_def_t sparc_def_t;
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/**
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* SPARCCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_phases: The parent class' reset phase handlers.
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*
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* A SPARC CPU model.
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*/
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struct SPARCCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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ResettablePhases parent_phases;
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sparc_def_t *cpu_def;
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};
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#endif
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