mirror of
https://github.com/qemu/qemu.git
synced 2024-12-19 10:13:43 +08:00
ba1ba5cca3
there are 2 use cases to deal with:
1: fixed CPU models per board/soc
2: boards with user configurable cpu_model and fallback to
default cpu_model if user hasn't specified one explicitly
For the 1st
drop intermediate cpu_model parsing and use const cpu type
directly, which replaces:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
object_new(typename)
with
object_new(FOO_CPU_TYPE_NAME)
or
cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
with
cpu_create(FOO_CPU_TYPE_NAME)
as result 1st use case doesn't have to invoke not necessary
translation and not needed code is removed.
For the 2nd
1: set default cpu type with MachineClass::default_cpu_type and
2: use generic cpu_model parsing that done before machine_init()
is run and:
2.1: drop custom cpu_model parsing where pattern is:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
[parse_features(typename, cpu_model, &err) ]
2.2: or replace cpu_generic_init() which does what
2.1 does + create_cpu(typename) with just
create_cpu(machine->cpu_type)
as result cpu_name -> cpu_type translation is done using
generic machine code one including parsing optional features
if supported/present (removes a bunch of duplicated cpu_model
parsing code) and default cpu type is defined in an uniform way
within machine_class_init callbacks instead of adhoc places
in boadr's machine_init code.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1505318697-77161-6-git-send-email-imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
|
|
* STM32F205 SoC
|
|
*
|
|
* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
* in the Software without restriction, including without limitation the rights
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
* furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
* THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef HW_ARM_STM32F205_SOC_H
|
|
#define HW_ARM_STM32F205_SOC_H
|
|
|
|
#include "hw/misc/stm32f2xx_syscfg.h"
|
|
#include "hw/timer/stm32f2xx_timer.h"
|
|
#include "hw/char/stm32f2xx_usart.h"
|
|
#include "hw/adc/stm32f2xx_adc.h"
|
|
#include "hw/or-irq.h"
|
|
#include "hw/ssi/stm32f2xx_spi.h"
|
|
#include "hw/arm/armv7m.h"
|
|
|
|
#define TYPE_STM32F205_SOC "stm32f205-soc"
|
|
#define STM32F205_SOC(obj) \
|
|
OBJECT_CHECK(STM32F205State, (obj), TYPE_STM32F205_SOC)
|
|
|
|
#define STM_NUM_USARTS 6
|
|
#define STM_NUM_TIMERS 4
|
|
#define STM_NUM_ADCS 3
|
|
#define STM_NUM_SPIS 3
|
|
|
|
#define FLASH_BASE_ADDRESS 0x08000000
|
|
#define FLASH_SIZE (1024 * 1024)
|
|
#define SRAM_BASE_ADDRESS 0x20000000
|
|
#define SRAM_SIZE (128 * 1024)
|
|
|
|
typedef struct STM32F205State {
|
|
/*< private >*/
|
|
SysBusDevice parent_obj;
|
|
/*< public >*/
|
|
|
|
char *cpu_type;
|
|
|
|
ARMv7MState armv7m;
|
|
|
|
STM32F2XXSyscfgState syscfg;
|
|
STM32F2XXUsartState usart[STM_NUM_USARTS];
|
|
STM32F2XXTimerState timer[STM_NUM_TIMERS];
|
|
STM32F2XXADCState adc[STM_NUM_ADCS];
|
|
STM32F2XXSPIState spi[STM_NUM_SPIS];
|
|
|
|
qemu_or_irq *adc_irqs;
|
|
} STM32F205State;
|
|
|
|
#endif
|