Igor Mammedov 1f3aba377d pc: acpi: drop intermediate PCMachineState.node_cpu ... PCMachineState.node_cpu was used for mapping APIC ID to numa node id as CPU entries in SRAT used to be built on sparse APIC ID bitmap (up to apic_id_limit). However since commit 5803fce pc: acpi: SRAT: create only valid processor lapic entries CPU entries in SRAT aren't build using apic bitmap but using 0..maxcpus index instead which is also used for creating numa_info[x].node_cpu map. So instead of doing useless intermediate conversion from 1. node by cpu index -> node by apic id i.e. numa_info[x].node_cpu -> PCMachineState.node_cpu 2. apic id -> srat entry PMX PCMachineState.node_cpu[apic id] -> PMX value use numa_info[x].node_cpu map directly like ARM does and do 1. numa_info[x].node_cpu -> PMX value using index in range 0..maxcpus and drop not necessary PCMachineState.node_cpu and related code. That also removes the last (not counting legacy hotplug) dependency of ACPI code on apic_id_limit and need to allocate huge sparse PCMachineState.node_cpu array in case of 32-bit APIC IDs. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2016-06-24 08:34:47 +03:00
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apic_internal.h	cpu/apic: drop icc bus/bridge	2015-10-02 16:22:02 -03:00
apic-msidef.h	hw: move headers to include/	2013-04-08 18:13:10 +02:00
apic.h	apic: move target-dependent definitions to cpu.h	2016-05-19 16:42:28 +02:00
ich9.h	ICH9: fix typo	2016-06-07 18:19:23 +03:00
intel_iommu.h	intel_iommu: large page support	2016-02-06 20:44:10 +02:00
ioapic_internal.h	ioapic: keep RO bits for IOAPIC entry	2016-05-23 16:53:43 +02:00
ioapic.h	pc: move IO_APIC_DEFAULT_ADDRESS to include/hw/i386/ioapic.h	2013-07-29 19:33:32 -05:00
pc.h	pc: acpi: drop intermediate PCMachineState.node_cpu	2016-06-24 08:34:47 +03:00
topology.h	include: Clean up includes	2016-02-23 12:43:05 +00:00