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a307d59434
Currently, the interfaces in the pseries machine code for assignment and setup of interrupts pass around qemu_irq objects. That was done in an attempt not to be too closely linked to the specific XICS interrupt controller. However interactions with the device tree setup made that attempt rather futile, and XICS is part of the PAPR spec anyway, so this really just meant we had to carry both the qemu_irq pointers and the XICS irq numbers around. This mess will just get worse when we add upcoming PCI MSI support, since that will require tracking a bunch more interrupt. Therefore, this patch reworks the spapr code to just use XICS irq numbers (roughly equivalent to GSIs on x86) and only retrieve the qemu_irq pointers from the XICS code when we need them (a trivial lookup). This is a reworked and generalized version of an earlier spapr_pci specific patch from Alexey Kardashevskiy. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix checkpath warning] Signed-off-by: Alexander Graf <agraf@suse.de>
561 lines
14 KiB
C
561 lines
14 KiB
C
/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
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*
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* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "hw.h"
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#include "hw/spapr.h"
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#include "hw/xics.h"
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/*
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* ICP: Presentation layer
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*/
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struct icp_server_state {
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uint32_t xirr;
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uint8_t pending_priority;
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uint8_t mfrr;
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qemu_irq output;
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};
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#define XISR_MASK 0x00ffffff
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#define CPPR_MASK 0xff000000
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#define XISR(ss) (((ss)->xirr) & XISR_MASK)
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#define CPPR(ss) (((ss)->xirr) >> 24)
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struct ics_state;
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struct icp_state {
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long nr_servers;
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struct icp_server_state *ss;
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struct ics_state *ics;
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};
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static void ics_reject(struct ics_state *ics, int nr);
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static void ics_resend(struct ics_state *ics);
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static void ics_eoi(struct ics_state *ics, int nr);
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static void icp_check_ipi(struct icp_state *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
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return;
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}
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
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ss->pending_priority = ss->mfrr;
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qemu_irq_raise(ss->output);
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}
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static void icp_resend(struct icp_state *icp, int server)
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{
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struct icp_server_state *ss = icp->ss + server;
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if (ss->mfrr < CPPR(ss)) {
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icp_check_ipi(icp, server);
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}
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ics_resend(icp->ics);
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}
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static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
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{
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struct icp_server_state *ss = icp->ss + server;
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uint8_t old_cppr;
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uint32_t old_xisr;
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old_cppr = CPPR(ss);
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
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if (cppr < old_cppr) {
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if (XISR(ss) && (cppr <= ss->pending_priority)) {
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old_xisr = XISR(ss);
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ss->xirr &= ~XISR_MASK; /* Clear XISR */
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qemu_irq_lower(ss->output);
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ics_reject(icp->ics, old_xisr);
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}
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} else {
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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}
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static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr)
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{
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struct icp_server_state *ss = icp->ss + nr;
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ss->mfrr = mfrr;
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if (mfrr < CPPR(ss)) {
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icp_check_ipi(icp, nr);
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}
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}
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static uint32_t icp_accept(struct icp_server_state *ss)
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{
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uint32_t xirr;
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qemu_irq_lower(ss->output);
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xirr = ss->xirr;
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ss->xirr = ss->pending_priority << 24;
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return xirr;
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}
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static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
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{
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struct icp_server_state *ss = icp->ss + server;
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/* Send EOI -> ICS */
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ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
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ics_eoi(icp->ics, xirr & XISR_MASK);
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if (!XISR(ss)) {
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icp_resend(icp, server);
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}
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}
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static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
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{
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struct icp_server_state *ss = icp->ss + server;
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if ((priority >= CPPR(ss))
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|| (XISR(ss) && (ss->pending_priority <= priority))) {
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ics_reject(icp->ics, nr);
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} else {
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if (XISR(ss)) {
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ics_reject(icp->ics, XISR(ss));
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}
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ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
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ss->pending_priority = priority;
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qemu_irq_raise(ss->output);
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}
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}
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/*
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* ICS: Source layer
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*/
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struct ics_irq_state {
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int server;
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uint8_t priority;
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uint8_t saved_priority;
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enum xics_irq_type type;
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int asserted:1;
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int sent:1;
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int rejected:1;
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int masked_pending:1;
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};
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struct ics_state {
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int nr_irqs;
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int offset;
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qemu_irq *qirqs;
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struct ics_irq_state *irqs;
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struct icp_state *icp;
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};
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static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
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{
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return (nr >= ics->offset)
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&& (nr < (ics->offset + ics->nr_irqs));
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}
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static void resend_msi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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/* FIXME: filter by server#? */
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if (irq->rejected) {
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irq->rejected = 0;
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if (irq->priority != 0xff) {
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icp_irq(ics->icp, irq->server, srcno + ics->offset,
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irq->priority);
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}
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}
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}
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static void resend_lsi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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if ((irq->priority != 0xff) && irq->asserted && !irq->sent) {
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irq->sent = 1;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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static void set_irq_msi(struct ics_state *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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if (val) {
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if (irq->priority == 0xff) {
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irq->masked_pending = 1;
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/* masked pending */ ;
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} else {
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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}
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}
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static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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irq->asserted = val;
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resend_lsi(ics, srcno);
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}
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static void ics_set_irq(void *opaque, int srcno, int val)
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{
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struct ics_state *ics = (struct ics_state *)opaque;
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struct ics_irq_state *irq = ics->irqs + srcno;
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if (irq->type == XICS_LSI) {
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set_irq_lsi(ics, srcno, val);
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} else {
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set_irq_msi(ics, srcno, val);
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}
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}
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static void write_xive_msi(struct ics_state *ics, int srcno)
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{
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struct ics_irq_state *irq = ics->irqs + srcno;
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if (!irq->masked_pending || (irq->priority == 0xff)) {
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return;
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}
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irq->masked_pending = 0;
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icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
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}
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static void write_xive_lsi(struct ics_state *ics, int srcno)
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{
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resend_lsi(ics, srcno);
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}
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static void ics_write_xive(struct ics_state *ics, int nr, int server,
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uint8_t priority)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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irq->server = server;
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irq->priority = priority;
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if (irq->type == XICS_LSI) {
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write_xive_lsi(ics, srcno);
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} else {
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write_xive_msi(ics, srcno);
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}
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}
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static void ics_reject(struct ics_state *ics, int nr)
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{
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struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
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irq->rejected = 1; /* Irrelevant but harmless for LSI */
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irq->sent = 0; /* Irrelevant but harmless for MSI */
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}
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static void ics_resend(struct ics_state *ics)
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{
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int i;
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for (i = 0; i < ics->nr_irqs; i++) {
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struct ics_irq_state *irq = ics->irqs + i;
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/* FIXME: filter by server#? */
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if (irq->type == XICS_LSI) {
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resend_lsi(ics, i);
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} else {
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resend_msi(ics, i);
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}
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}
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}
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static void ics_eoi(struct ics_state *ics, int nr)
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{
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int srcno = nr - ics->offset;
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struct ics_irq_state *irq = ics->irqs + srcno;
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if (irq->type == XICS_LSI) {
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irq->sent = 0;
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}
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}
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/*
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* Exported functions
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*/
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qemu_irq xics_get_qirq(struct icp_state *icp, int irq)
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{
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if ((irq < icp->ics->offset)
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|| (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
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return NULL;
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}
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return icp->ics->qirqs[irq - icp->ics->offset];
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}
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void xics_set_irq_type(struct icp_state *icp, int irq,
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enum xics_irq_type type)
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{
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assert((irq >= icp->ics->offset)
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&& (irq < (icp->ics->offset + icp->ics->nr_irqs)));
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assert((type == XICS_MSI) || (type == XICS_LSI));
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icp->ics->irqs[irq - icp->ics->offset].type = type;
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}
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static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong cppr = args[0];
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icp_set_cppr(spapr->icp, env->cpu_index, cppr);
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return H_SUCCESS;
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}
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static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong server = args[0];
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target_ulong mfrr = args[1];
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if (server >= spapr->icp->nr_servers) {
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return H_PARAMETER;
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}
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icp_set_mfrr(spapr->icp, server, mfrr);
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return H_SUCCESS;
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}
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static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
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args[0] = xirr;
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return H_SUCCESS;
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}
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static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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target_ulong xirr = args[0];
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icp_eoi(spapr->icp, env->cpu_index, xirr);
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return H_SUCCESS;
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}
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static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr, server, priority;
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if ((nargs != 3) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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server = rtas_ld(args, 1);
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priority = rtas_ld(args, 2);
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if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
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|| (priority > 0xff)) {
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rtas_st(rets, 0, -3);
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return;
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}
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ics_write_xive(ics, nr, server, priority);
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rtas_st(rets, 0, 0); /* Success */
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}
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static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 3)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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rtas_st(rets, 0, 0); /* Success */
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rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
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rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
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}
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static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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/* This is a NOP for now, since the described PAPR semantics don't
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* seem to gel with what Linux does */
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#if 0
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struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
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irq->saved_priority = irq->priority;
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ics_write_xive_msi(xics, nr, irq->server, 0xff);
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#endif
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rtas_st(rets, 0, 0); /* Success */
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}
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static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
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uint32_t nargs, target_ulong args,
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uint32_t nret, target_ulong rets)
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{
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struct ics_state *ics = spapr->icp->ics;
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uint32_t nr;
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if ((nargs != 1) || (nret != 1)) {
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rtas_st(rets, 0, -3);
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return;
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}
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nr = rtas_ld(args, 0);
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if (!ics_valid_irq(ics, nr)) {
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rtas_st(rets, 0, -3);
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return;
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}
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/* This is a NOP for now, since the described PAPR semantics don't
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* seem to gel with what Linux does */
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#if 0
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struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
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ics_write_xive_msi(xics, nr, irq->server, irq->saved_priority);
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#endif
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rtas_st(rets, 0, 0); /* Success */
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}
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struct icp_state *xics_system_init(int nr_irqs)
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{
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CPUPPCState *env;
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int max_server_num;
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int i;
|
|
struct icp_state *icp;
|
|
struct ics_state *ics;
|
|
|
|
max_server_num = -1;
|
|
for (env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
if (env->cpu_index > max_server_num) {
|
|
max_server_num = env->cpu_index;
|
|
}
|
|
}
|
|
|
|
icp = g_malloc0(sizeof(*icp));
|
|
icp->nr_servers = max_server_num + 1;
|
|
icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
|
|
|
|
for (i = 0; i < icp->nr_servers; i++) {
|
|
icp->ss[i].mfrr = 0xff;
|
|
}
|
|
|
|
for (env = first_cpu; env != NULL; env = env->next_cpu) {
|
|
struct icp_server_state *ss = &icp->ss[env->cpu_index];
|
|
|
|
switch (PPC_INPUT(env)) {
|
|
case PPC_FLAGS_INPUT_POWER7:
|
|
ss->output = env->irq_inputs[POWER7_INPUT_INT];
|
|
break;
|
|
|
|
case PPC_FLAGS_INPUT_970:
|
|
ss->output = env->irq_inputs[PPC970_INPUT_INT];
|
|
break;
|
|
|
|
default:
|
|
hw_error("XICS interrupt model does not support this CPU bus "
|
|
"model\n");
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
ics = g_malloc0(sizeof(*ics));
|
|
ics->nr_irqs = nr_irqs;
|
|
ics->offset = 16;
|
|
ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
|
|
|
|
icp->ics = ics;
|
|
ics->icp = icp;
|
|
|
|
for (i = 0; i < nr_irqs; i++) {
|
|
ics->irqs[i].priority = 0xff;
|
|
ics->irqs[i].saved_priority = 0xff;
|
|
}
|
|
|
|
ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
|
|
|
|
spapr_register_hypercall(H_CPPR, h_cppr);
|
|
spapr_register_hypercall(H_IPI, h_ipi);
|
|
spapr_register_hypercall(H_XIRR, h_xirr);
|
|
spapr_register_hypercall(H_EOI, h_eoi);
|
|
|
|
spapr_rtas_register("ibm,set-xive", rtas_set_xive);
|
|
spapr_rtas_register("ibm,get-xive", rtas_get_xive);
|
|
spapr_rtas_register("ibm,int-off", rtas_int_off);
|
|
spapr_rtas_register("ibm,int-on", rtas_int_on);
|
|
|
|
return icp;
|
|
}
|