mirror of
https://github.com/qemu/qemu.git
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3054434d61
Signed-off-by: Avi Kivity <avi@redhat.com>
826 lines
21 KiB
C
826 lines
21 KiB
C
/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2009 Herve Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "mips.h"
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#include "qemu-timer.h"
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/********************************************************/
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/* debug rc4030 */
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//#define DEBUG_RC4030
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//#define DEBUG_RC4030_DMA
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#ifdef DEBUG_RC4030
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#define DPRINTF(fmt, ...) \
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do { printf("rc4030: " fmt , ## __VA_ARGS__); } while (0)
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static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
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"network", "scsi", "keyboard", "mouse", "serial0", "serial1" };
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#else
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#define DPRINTF(fmt, ...)
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#endif
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#define RC4030_ERROR(fmt, ...) \
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do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* rc4030 emulation */
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typedef struct dma_pagetable_entry {
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int32_t frame;
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int32_t owner;
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} QEMU_PACKED dma_pagetable_entry;
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#define DMA_PAGESIZE 4096
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#define DMA_REG_ENABLE 1
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#define DMA_REG_COUNT 2
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#define DMA_REG_ADDRESS 3
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#define DMA_FLAG_ENABLE 0x0001
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#define DMA_FLAG_MEM_TO_DEV 0x0002
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#define DMA_FLAG_TC_INTR 0x0100
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#define DMA_FLAG_MEM_INTR 0x0200
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#define DMA_FLAG_ADDR_INTR 0x0400
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typedef struct rc4030State
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{
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t revision; /* 0x0008: RC4030 Revision register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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/* DMA */
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uint32_t dma_regs[8][4];
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uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
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uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
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/* cache */
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uint32_t cache_maint; /* 0x0030: Cache Maintenance */
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uint32_t remote_failed_address; /* 0x0038: Remote Failed Address */
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uint32_t memory_failed_address; /* 0x0040: Memory Failed Address */
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uint32_t cache_ptag; /* 0x0048: I/O Cache Physical Tag */
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uint32_t cache_ltag; /* 0x0050: I/O Cache Logical Tag */
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uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */
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uint32_t nmi_interrupt; /* 0x0200: interrupt source */
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uint32_t offset210;
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uint32_t nvram_protect; /* 0x0220: NV ram protect register */
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uint32_t rem_speed[16];
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uint32_t imr_jazz; /* Local bus int enable mask */
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uint32_t isr_jazz; /* Local bus int source */
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/* timer */
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QEMUTimer *periodic_timer;
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uint32_t itr; /* Interval timer reload */
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qemu_irq timer_irq;
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qemu_irq jazz_bus_irq;
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MemoryRegion iomem_chipset;
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MemoryRegion iomem_jazzio;
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} rc4030State;
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static void set_next_tick(rc4030State *s)
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{
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qemu_irq_lower(s->timer_irq);
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uint32_t tm_hz;
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tm_hz = 1000 / (s->itr + 1);
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qemu_mod_timer(s->periodic_timer, qemu_get_clock_ns(vm_clock) +
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get_ticks_per_sec() / tm_hz);
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}
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/* called for accesses to rc4030 */
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static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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addr &= 0x3fff;
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switch (addr & ~0x3) {
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/* Global config register */
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case 0x0000:
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val = s->config;
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break;
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/* Revision register */
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case 0x0008:
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val = s->revision;
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break;
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/* Invalid Address register */
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case 0x0010:
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val = s->invalid_address_register;
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break;
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/* DMA transl. table base */
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case 0x0018:
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val = s->dma_tl_base;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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val = s->dma_tl_limit;
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break;
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/* Remote Failed Address */
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case 0x0038:
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val = s->remote_failed_address;
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break;
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/* Memory Failed Address */
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case 0x0040:
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val = s->memory_failed_address;
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break;
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/* I/O Cache Byte Mask */
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case 0x0058:
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val = s->cache_bmask;
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/* HACK */
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if (s->cache_bmask == (uint32_t)-1)
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s->cache_bmask = 0;
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break;
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/* Remote Speed Registers */
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case 0x0070:
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case 0x0078:
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case 0x0080:
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case 0x0088:
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case 0x0090:
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case 0x0098:
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case 0x00a0:
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case 0x00a8:
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case 0x00b0:
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case 0x00b8:
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case 0x00c0:
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case 0x00c8:
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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case 0x00e8:
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val = s->rem_speed[(addr - 0x0070) >> 3];
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break;
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/* DMA channel base address */
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case 0x0100:
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case 0x0108:
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case 0x0110:
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case 0x0118:
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case 0x0120:
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case 0x0128:
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case 0x0130:
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case 0x0138:
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case 0x0140:
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case 0x0148:
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case 0x0150:
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case 0x0158:
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case 0x0160:
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case 0x0168:
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case 0x0170:
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case 0x0178:
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case 0x0180:
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case 0x0188:
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case 0x0190:
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case 0x0198:
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case 0x01a0:
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case 0x01a8:
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case 0x01b0:
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case 0x01b8:
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case 0x01c0:
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case 0x01c8:
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x01e8:
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case 0x01f0:
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case 0x01f8:
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{
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int entry = (addr - 0x0100) >> 5;
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int idx = (addr & 0x1f) >> 3;
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val = s->dma_regs[entry][idx];
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}
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break;
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/* Interrupt source */
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case 0x0200:
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val = s->nmi_interrupt;
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break;
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/* Error type */
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case 0x0208:
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val = 0;
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break;
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/* Offset 0x0210 */
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case 0x0210:
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val = s->offset210;
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break;
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/* NV ram protect register */
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case 0x0220:
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val = s->nvram_protect;
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break;
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/* Interval timer count */
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case 0x0230:
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val = 0;
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qemu_irq_lower(s->timer_irq);
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break;
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/* EISA interrupt */
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case 0x0238:
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val = 7; /* FIXME: should be read from EISA controller */
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break;
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default:
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RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr);
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val = 0;
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break;
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}
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if ((addr & ~3) != 0x230) {
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DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr);
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}
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return val;
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}
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static uint32_t rc4030_readw(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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if (addr & 0x2)
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return v >> 16;
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else
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return v & 0xffff;
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}
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static uint32_t rc4030_readb(void *opaque, target_phys_addr_t addr)
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{
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uint32_t v = rc4030_readl(opaque, addr & ~0x3);
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return (v >> (8 * (addr & 0x3))) & 0xff;
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}
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static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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rc4030State *s = opaque;
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addr &= 0x3fff;
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DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr);
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switch (addr & ~0x3) {
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/* Global config register */
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case 0x0000:
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s->config = val;
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break;
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/* DMA transl. table base */
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case 0x0018:
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s->dma_tl_base = val;
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break;
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/* DMA transl. table limit */
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case 0x0020:
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s->dma_tl_limit = val;
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break;
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/* DMA transl. table invalidated */
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case 0x0028:
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break;
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/* Cache Maintenance */
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case 0x0030:
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s->cache_maint = val;
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break;
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/* I/O Cache Physical Tag */
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case 0x0048:
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s->cache_ptag = val;
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break;
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/* I/O Cache Logical Tag */
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case 0x0050:
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s->cache_ltag = val;
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break;
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/* I/O Cache Byte Mask */
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case 0x0058:
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s->cache_bmask |= val; /* HACK */
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break;
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/* I/O Cache Buffer Window */
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case 0x0060:
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/* HACK */
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if (s->cache_ltag == 0x80000001 && s->cache_bmask == 0xf0f0f0f) {
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target_phys_addr_t dest = s->cache_ptag & ~0x1;
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dest += (s->cache_maint & 0x3) << 3;
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cpu_physical_memory_write(dest, &val, 4);
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}
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break;
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/* Remote Speed Registers */
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case 0x0070:
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case 0x0078:
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case 0x0080:
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case 0x0088:
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case 0x0090:
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case 0x0098:
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case 0x00a0:
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case 0x00a8:
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case 0x00b0:
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case 0x00b8:
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case 0x00c0:
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case 0x00c8:
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case 0x00d0:
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case 0x00d8:
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case 0x00e0:
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case 0x00e8:
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s->rem_speed[(addr - 0x0070) >> 3] = val;
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break;
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/* DMA channel base address */
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case 0x0100:
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case 0x0108:
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case 0x0110:
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case 0x0118:
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case 0x0120:
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case 0x0128:
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case 0x0130:
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case 0x0138:
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case 0x0140:
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case 0x0148:
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case 0x0150:
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case 0x0158:
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case 0x0160:
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case 0x0168:
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case 0x0170:
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case 0x0178:
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case 0x0180:
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case 0x0188:
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case 0x0190:
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case 0x0198:
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case 0x01a0:
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case 0x01a8:
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case 0x01b0:
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case 0x01b8:
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case 0x01c0:
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case 0x01c8:
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case 0x01d0:
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case 0x01d8:
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case 0x01e0:
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case 0x01e8:
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case 0x01f0:
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case 0x01f8:
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{
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int entry = (addr - 0x0100) >> 5;
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int idx = (addr & 0x1f) >> 3;
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s->dma_regs[entry][idx] = val;
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}
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break;
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/* Offset 0x0210 */
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case 0x0210:
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s->offset210 = val;
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break;
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/* Interval timer reload */
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case 0x0228:
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s->itr = val;
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qemu_irq_lower(s->timer_irq);
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set_next_tick(s);
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break;
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/* EISA interrupt */
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case 0x0238:
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break;
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default:
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RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr);
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break;
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}
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}
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static void rc4030_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
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if (addr & 0x2)
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val = (val << 16) | (old_val & 0x0000ffff);
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else
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val = val | (old_val & 0xffff0000);
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rc4030_writel(opaque, addr & ~0x3, val);
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}
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static void rc4030_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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uint32_t old_val = rc4030_readl(opaque, addr & ~0x3);
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switch (addr & 3) {
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case 0:
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val = val | (old_val & 0xffffff00);
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break;
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case 1:
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val = (val << 8) | (old_val & 0xffff00ff);
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break;
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case 2:
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val = (val << 16) | (old_val & 0xff00ffff);
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break;
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case 3:
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val = (val << 24) | (old_val & 0x00ffffff);
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break;
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}
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rc4030_writel(opaque, addr & ~0x3, val);
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}
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static const MemoryRegionOps rc4030_ops = {
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.old_mmio = {
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.read = { rc4030_readb, rc4030_readw, rc4030_readl, },
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.write = { rc4030_writeb, rc4030_writew, rc4030_writel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void update_jazz_irq(rc4030State *s)
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{
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uint16_t pending;
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pending = s->isr_jazz & s->imr_jazz;
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#ifdef DEBUG_RC4030
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if (s->isr_jazz != 0) {
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uint32_t irq = 0;
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DPRINTF("pending irqs:");
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for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
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if (s->isr_jazz & (1 << irq)) {
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printf(" %s", irq_names[irq]);
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if (!(s->imr_jazz & (1 << irq))) {
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printf("(ignored)");
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}
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}
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}
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printf("\n");
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}
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#endif
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if (pending != 0)
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qemu_irq_raise(s->jazz_bus_irq);
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else
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qemu_irq_lower(s->jazz_bus_irq);
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}
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static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
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{
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rc4030State *s = opaque;
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if (level) {
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s->isr_jazz |= 1 << irq;
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} else {
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s->isr_jazz &= ~(1 << irq);
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}
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update_jazz_irq(s);
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}
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static void rc4030_periodic_timer(void *opaque)
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{
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rc4030State *s = opaque;
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set_next_tick(s);
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qemu_irq_raise(s->timer_irq);
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}
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|
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static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
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{
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rc4030State *s = opaque;
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uint32_t val;
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uint32_t irq;
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addr &= 0xfff;
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switch (addr) {
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/* Local bus int source */
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case 0x00: {
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uint32_t pending = s->isr_jazz & s->imr_jazz;
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val = 0;
|
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irq = 0;
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while (pending) {
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if (pending & 1) {
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DPRINTF("returning irq %s\n", irq_names[irq]);
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val = (irq + 1) << 2;
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break;
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}
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irq++;
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pending >>= 1;
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}
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break;
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}
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|
/* Local bus int enable mask */
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case 0x02:
|
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val = s->imr_jazz;
|
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break;
|
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default:
|
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RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
|
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val = 0;
|
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}
|
|
|
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DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr);
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|
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return val;
|
|
}
|
|
|
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static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr)
|
|
{
|
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uint32_t v;
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v = jazzio_readw(opaque, addr & ~0x1);
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|
return (v >> (8 * (addr & 0x1))) & 0xff;
|
|
}
|
|
|
|
static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
|
|
{
|
|
uint32_t v;
|
|
v = jazzio_readw(opaque, addr);
|
|
v |= jazzio_readw(opaque, addr + 2) << 16;
|
|
return v;
|
|
}
|
|
|
|
static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
rc4030State *s = opaque;
|
|
addr &= 0xfff;
|
|
|
|
DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
|
|
|
|
switch (addr) {
|
|
/* Local bus int enable mask */
|
|
case 0x02:
|
|
s->imr_jazz = val;
|
|
update_jazz_irq(s);
|
|
break;
|
|
default:
|
|
RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
uint32_t old_val = jazzio_readw(opaque, addr & ~0x1);
|
|
|
|
switch (addr & 1) {
|
|
case 0:
|
|
val = val | (old_val & 0xff00);
|
|
break;
|
|
case 1:
|
|
val = (val << 8) | (old_val & 0x00ff);
|
|
break;
|
|
}
|
|
jazzio_writew(opaque, addr & ~0x1, val);
|
|
}
|
|
|
|
static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
|
|
{
|
|
jazzio_writew(opaque, addr, val & 0xffff);
|
|
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
|
|
}
|
|
|
|
static const MemoryRegionOps jazzio_ops = {
|
|
.old_mmio = {
|
|
.read = { jazzio_readb, jazzio_readw, jazzio_readl, },
|
|
.write = { jazzio_writeb, jazzio_writew, jazzio_writel, },
|
|
},
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void rc4030_reset(void *opaque)
|
|
{
|
|
rc4030State *s = opaque;
|
|
int i;
|
|
|
|
s->config = 0x410; /* some boards seem to accept 0x104 too */
|
|
s->revision = 1;
|
|
s->invalid_address_register = 0;
|
|
|
|
memset(s->dma_regs, 0, sizeof(s->dma_regs));
|
|
s->dma_tl_base = s->dma_tl_limit = 0;
|
|
|
|
s->remote_failed_address = s->memory_failed_address = 0;
|
|
s->cache_maint = 0;
|
|
s->cache_ptag = s->cache_ltag = 0;
|
|
s->cache_bmask = 0;
|
|
|
|
s->offset210 = 0x18186;
|
|
s->nvram_protect = 7;
|
|
for (i = 0; i < 15; i++)
|
|
s->rem_speed[i] = 7;
|
|
s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
|
|
s->isr_jazz = 0;
|
|
|
|
s->itr = 0;
|
|
|
|
qemu_irq_lower(s->timer_irq);
|
|
qemu_irq_lower(s->jazz_bus_irq);
|
|
}
|
|
|
|
static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
|
|
{
|
|
rc4030State* s = opaque;
|
|
int i, j;
|
|
|
|
if (version_id != 2)
|
|
return -EINVAL;
|
|
|
|
s->config = qemu_get_be32(f);
|
|
s->invalid_address_register = qemu_get_be32(f);
|
|
for (i = 0; i < 8; i++)
|
|
for (j = 0; j < 4; j++)
|
|
s->dma_regs[i][j] = qemu_get_be32(f);
|
|
s->dma_tl_base = qemu_get_be32(f);
|
|
s->dma_tl_limit = qemu_get_be32(f);
|
|
s->cache_maint = qemu_get_be32(f);
|
|
s->remote_failed_address = qemu_get_be32(f);
|
|
s->memory_failed_address = qemu_get_be32(f);
|
|
s->cache_ptag = qemu_get_be32(f);
|
|
s->cache_ltag = qemu_get_be32(f);
|
|
s->cache_bmask = qemu_get_be32(f);
|
|
s->offset210 = qemu_get_be32(f);
|
|
s->nvram_protect = qemu_get_be32(f);
|
|
for (i = 0; i < 15; i++)
|
|
s->rem_speed[i] = qemu_get_be32(f);
|
|
s->imr_jazz = qemu_get_be32(f);
|
|
s->isr_jazz = qemu_get_be32(f);
|
|
s->itr = qemu_get_be32(f);
|
|
|
|
set_next_tick(s);
|
|
update_jazz_irq(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rc4030_save(QEMUFile *f, void *opaque)
|
|
{
|
|
rc4030State* s = opaque;
|
|
int i, j;
|
|
|
|
qemu_put_be32(f, s->config);
|
|
qemu_put_be32(f, s->invalid_address_register);
|
|
for (i = 0; i < 8; i++)
|
|
for (j = 0; j < 4; j++)
|
|
qemu_put_be32(f, s->dma_regs[i][j]);
|
|
qemu_put_be32(f, s->dma_tl_base);
|
|
qemu_put_be32(f, s->dma_tl_limit);
|
|
qemu_put_be32(f, s->cache_maint);
|
|
qemu_put_be32(f, s->remote_failed_address);
|
|
qemu_put_be32(f, s->memory_failed_address);
|
|
qemu_put_be32(f, s->cache_ptag);
|
|
qemu_put_be32(f, s->cache_ltag);
|
|
qemu_put_be32(f, s->cache_bmask);
|
|
qemu_put_be32(f, s->offset210);
|
|
qemu_put_be32(f, s->nvram_protect);
|
|
for (i = 0; i < 15; i++)
|
|
qemu_put_be32(f, s->rem_speed[i]);
|
|
qemu_put_be32(f, s->imr_jazz);
|
|
qemu_put_be32(f, s->isr_jazz);
|
|
qemu_put_be32(f, s->itr);
|
|
}
|
|
|
|
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
|
|
{
|
|
rc4030State *s = opaque;
|
|
target_phys_addr_t entry_addr;
|
|
target_phys_addr_t phys_addr;
|
|
dma_pagetable_entry entry;
|
|
int index;
|
|
int ncpy, i;
|
|
|
|
i = 0;
|
|
for (;;) {
|
|
if (i == len) {
|
|
break;
|
|
}
|
|
|
|
ncpy = DMA_PAGESIZE - (addr & (DMA_PAGESIZE - 1));
|
|
if (ncpy > len - i)
|
|
ncpy = len - i;
|
|
|
|
/* Get DMA translation table entry */
|
|
index = addr / DMA_PAGESIZE;
|
|
if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) {
|
|
break;
|
|
}
|
|
entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry);
|
|
/* XXX: not sure. should we really use only lowest bits? */
|
|
entry_addr &= 0x7fffffff;
|
|
cpu_physical_memory_read(entry_addr, &entry, sizeof(entry));
|
|
|
|
/* Read/write data at right place */
|
|
phys_addr = entry.frame + (addr & (DMA_PAGESIZE - 1));
|
|
cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write);
|
|
|
|
i += ncpy;
|
|
addr += ncpy;
|
|
}
|
|
}
|
|
|
|
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
|
|
{
|
|
rc4030State *s = opaque;
|
|
target_phys_addr_t dma_addr;
|
|
int dev_to_mem;
|
|
|
|
s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
|
|
|
|
/* Check DMA channel consistency */
|
|
dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
|
|
if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) ||
|
|
(is_write != dev_to_mem)) {
|
|
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR;
|
|
s->nmi_interrupt |= 1 << n;
|
|
return;
|
|
}
|
|
|
|
/* Get start address and len */
|
|
if (len > s->dma_regs[n][DMA_REG_COUNT])
|
|
len = s->dma_regs[n][DMA_REG_COUNT];
|
|
dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
|
|
|
|
/* Read/write data at right place */
|
|
rc4030_dma_memory_rw(opaque, dma_addr, buf, len, is_write);
|
|
|
|
s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR;
|
|
s->dma_regs[n][DMA_REG_COUNT] -= len;
|
|
|
|
#ifdef DEBUG_RC4030_DMA
|
|
{
|
|
int i, j;
|
|
printf("rc4030 dma: Copying %d bytes %s host %p\n",
|
|
len, is_write ? "from" : "to", buf);
|
|
for (i = 0; i < len; i += 16) {
|
|
int n = 16;
|
|
if (n > len - i) {
|
|
n = len - i;
|
|
}
|
|
for (j = 0; j < n; j++)
|
|
printf("%02x ", buf[i + j]);
|
|
while (j++ < 16)
|
|
printf(" ");
|
|
printf("| ");
|
|
for (j = 0; j < n; j++)
|
|
printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.');
|
|
printf("\n");
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
struct rc4030DMAState {
|
|
void *opaque;
|
|
int n;
|
|
};
|
|
|
|
void rc4030_dma_read(void *dma, uint8_t *buf, int len)
|
|
{
|
|
rc4030_dma s = dma;
|
|
rc4030_do_dma(s->opaque, s->n, buf, len, 0);
|
|
}
|
|
|
|
void rc4030_dma_write(void *dma, uint8_t *buf, int len)
|
|
{
|
|
rc4030_dma s = dma;
|
|
rc4030_do_dma(s->opaque, s->n, buf, len, 1);
|
|
}
|
|
|
|
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
|
|
{
|
|
rc4030_dma *s;
|
|
struct rc4030DMAState *p;
|
|
int i;
|
|
|
|
s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
|
|
p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
|
|
for (i = 0; i < n; i++) {
|
|
p->opaque = opaque;
|
|
p->n = i;
|
|
s[i] = p;
|
|
p++;
|
|
}
|
|
return s;
|
|
}
|
|
|
|
void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
|
|
qemu_irq **irqs, rc4030_dma **dmas,
|
|
MemoryRegion *sysmem)
|
|
{
|
|
rc4030State *s;
|
|
|
|
s = g_malloc0(sizeof(rc4030State));
|
|
|
|
*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
|
|
*dmas = rc4030_allocate_dmas(s, 4);
|
|
|
|
s->periodic_timer = qemu_new_timer_ns(vm_clock, rc4030_periodic_timer, s);
|
|
s->timer_irq = timer;
|
|
s->jazz_bus_irq = jazz_bus;
|
|
|
|
qemu_register_reset(rc4030_reset, s);
|
|
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
|
|
rc4030_reset(s);
|
|
|
|
memory_region_init_io(&s->iomem_chipset, &rc4030_ops, s,
|
|
"rc4030.chipset", 0x300);
|
|
memory_region_add_subregion(sysmem, 0x80000000, &s->iomem_chipset);
|
|
memory_region_init_io(&s->iomem_jazzio, &jazzio_ops, s,
|
|
"rc4030.jazzio", 0x00001000);
|
|
memory_region_add_subregion(sysmem, 0xf0000000, &s->iomem_jazzio);
|
|
|
|
return s;
|
|
}
|