mirror of
https://github.com/qemu/qemu.git
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6c84ce0dc7
Register is one byte-wide (as per specification), so there is no need to specify endianness. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> [AF: Limit access validity to size 1] Signed-off-by: Andreas Färber <andreas.faerber@web.de>
200 lines
5.7 KiB
C
200 lines
5.7 KiB
C
/*
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* QEMU PREP PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "pc.h"
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#include "exec-memory.h"
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typedef struct PRePPCIState {
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PCIHostState host_state;
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MemoryRegion intack;
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qemu_irq irq[4];
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} PREPPCIState;
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typedef struct RavenPCIState {
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PCIDevice dev;
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} RavenPCIState;
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static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
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{
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int i;
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for(i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0)
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break;
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}
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return (addr & 0x7ff) | (i << 11);
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}
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static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned int size)
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{
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PREPPCIState *s = opaque;
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pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, size);
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}
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static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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PREPPCIState *s = opaque;
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return pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), size);
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}
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static const MemoryRegionOps PPC_PCIIO_ops = {
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.read = ppc_pci_io_read,
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.write = ppc_pci_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr,
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unsigned int size)
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{
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return pic_read_irq(isa_pic);
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}
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static const MemoryRegionOps PPC_intack_ops = {
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.read = ppc_intack_read,
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.valid = {
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.max_access_size = 1,
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},
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};
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static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 1;
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}
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static void prep_set_irq(void *opaque, int irq_num, int level)
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{
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qemu_irq *pic = opaque;
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qemu_set_irq(pic[irq_num] , level);
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}
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static int raven_pcihost_init(SysBusDevice *dev)
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{
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PCIHostState *h = FROM_SYSBUS(PCIHostState, dev);
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PREPPCIState *s = DO_UPCAST(PREPPCIState, host_state, h);
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *address_space_io = get_system_io();
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PCIBus *bus;
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int i;
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for (i = 0; i < 4; i++) {
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sysbus_init_irq(dev, &s->irq[i]);
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}
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bus = pci_register_bus(&h->busdev.qdev, NULL,
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prep_set_irq, prep_map_irq, s->irq,
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address_space_mem, address_space_io, 0, 4);
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h->bus = bus;
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memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
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"pci-conf-idx", 1);
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sysbus_add_io(dev, 0xcf8, &h->conf_mem);
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sysbus_init_ioports(&h->busdev, 0xcf8, 1);
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memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
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"pci-conf-data", 1);
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sysbus_add_io(dev, 0xcfc, &h->data_mem);
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sysbus_init_ioports(&h->busdev, 0xcfc, 1);
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memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
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memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
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memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1);
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memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
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pci_create_simple(bus, 0, "raven");
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return 0;
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}
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static int raven_init(PCIDevice *d)
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{
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d->config[0x0C] = 0x08; // cache_line_size
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d->config[0x0D] = 0x10; // latency_timer
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d->config[0x34] = 0x00; // capabilities_pointer
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return 0;
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}
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static const VMStateDescription vmstate_raven = {
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.name = "raven",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, RavenPCIState),
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VMSTATE_END_OF_LIST()
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},
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};
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static void raven_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = raven_init;
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k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
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k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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dc->desc = "PReP Host Bridge - Motorola Raven";
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dc->vmsd = &vmstate_raven;
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dc->no_user = 1;
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}
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static TypeInfo raven_info = {
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.name = "raven",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(RavenPCIState),
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.class_init = raven_class_init,
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};
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static void raven_pcihost_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = raven_pcihost_init;
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dc->fw_name = "pci";
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dc->no_user = 1;
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}
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static TypeInfo raven_pcihost_info = {
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.name = "raven-pcihost",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PREPPCIState),
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.class_init = raven_pcihost_class_init,
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};
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static void raven_register_types(void)
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{
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type_register_static(&raven_pcihost_info);
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type_register_static(&raven_info);
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}
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type_init(raven_register_types)
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