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182fbbf218
Allows us to use cpu_reset() in place of cpu_state_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Alexander Graf <agraf@suse.de>
305 lines
9.4 KiB
C
305 lines
9.4 KiB
C
/*
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* QEMU PowerPC 440 Bamboo board emulation
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*
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* Copyright 2007 IBM Corporation.
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* Authors:
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* Jerone Young <jyoung5@us.ibm.com>
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* Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
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* Hollis Blanchard <hollisb@us.ibm.com>
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "net.h"
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#include "hw.h"
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#include "pci.h"
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#include "boards.h"
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#include "kvm.h"
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#include "kvm_ppc.h"
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#include "device_tree.h"
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#include "loader.h"
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#include "elf.h"
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#include "exec-memory.h"
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#include "pc.h"
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#include "ppc.h"
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#include "ppc405.h"
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#include "sysemu.h"
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#include "sysbus.h"
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#define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
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/* from u-boot */
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#define KERNEL_ADDR 0x1000000
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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#define PPC440EP_PCI_CONFIG 0xeec00000
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#define PPC440EP_PCI_INTACK 0xeed00000
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#define PPC440EP_PCI_SPECIAL 0xeed00000
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#define PPC440EP_PCI_REGS 0xef400000
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#define PPC440EP_PCI_IO 0xe8000000
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#define PPC440EP_PCI_IOLEN 0x00010000
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#define PPC440EP_SDRAM_NR_BANKS 4
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static const unsigned int ppc440ep_sdram_bank_sizes[] = {
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256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
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};
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static target_phys_addr_t entry;
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static int bamboo_load_device_tree(target_phys_addr_t addr,
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uint32_t ramsize,
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target_phys_addr_t initrd_base,
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target_phys_addr_t initrd_size,
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const char *kernel_cmdline)
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{
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int ret = -1;
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#ifdef CONFIG_FDT
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uint32_t mem_reg_property[] = { 0, 0, ramsize };
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char *filename;
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int fdt_size;
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void *fdt;
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uint32_t tb_freq = 400000000;
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uint32_t clock_freq = 400000000;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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goto out;
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}
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fdt = load_device_tree(filename, &fdt_size);
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g_free(filename);
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if (fdt == NULL) {
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goto out;
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}
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/* Manipulate device tree in memory. */
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ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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if (ret < 0)
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fprintf(stderr, "couldn't set /memory/reg\n");
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
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initrd_base);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
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ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
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ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
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kernel_cmdline);
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if (ret < 0)
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fprintf(stderr, "couldn't set /chosen/bootargs\n");
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/* Copy data from the host device tree into the guest. Since the guest can
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* directly access the timebase without host involvement, we must expose
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* the correct frequencies. */
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if (kvm_enabled()) {
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tb_freq = kvmppc_get_tbfreq();
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clock_freq = kvmppc_get_clockfreq();
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}
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qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
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clock_freq);
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qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
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tb_freq);
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ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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out:
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#endif
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return ret;
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}
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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target_phys_addr_t pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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tlb = &env->tlb.tlbe[1];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0xffffffff */
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tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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cpu_reset(CPU(cpu));
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env->gpr[1] = (16<<20) - 8;
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env->gpr[3] = FDT_ADDR;
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env->nip = entry;
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/* Create a mapping for the kernel. */
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mmubooke_create_initial_mapping(env, 0, 0);
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}
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static void bamboo_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ram_memories
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= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
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target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
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target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
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qemu_irq *pic;
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qemu_irq *irqs;
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PCIBus *pcibus;
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PowerPCCPU *cpu;
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CPUPPCState *env;
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uint64_t elf_entry;
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uint64_t elf_lowaddr;
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target_phys_addr_t loadaddr = 0;
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target_long initrd_size = 0;
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DeviceState *dev;
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int success;
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int i;
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/* Setup CPU. */
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if (cpu_model == NULL) {
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cpu_model = "440EP";
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}
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cpu = cpu_ppc_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "Unable to initialize CPU!\n");
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exit(1);
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}
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env = &cpu->env;
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qemu_register_reset(main_cpu_reset, cpu);
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ppc_booke_timers_init(env, 400000000, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* interrupt controller */
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irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
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/* SDRAM controller */
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memset(ram_bases, 0, sizeof(ram_bases));
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memset(ram_sizes, 0, sizeof(ram_sizes));
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ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
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ram_memories,
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ram_bases, ram_sizes,
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ppc440ep_sdram_bank_sizes);
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/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
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ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, 1);
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/* PCI */
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dev = sysbus_create_varargs("ppc4xx-pcihost", PPC440EP_PCI_CONFIG,
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pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
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pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
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NULL);
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pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pcibus) {
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fprintf(stderr, "couldn't create PCI controller!\n");
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exit(1);
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}
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isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
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if (serial_hds[0] != NULL) {
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serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hds[1] != NULL) {
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serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
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PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
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DEVICE_BIG_ENDIAN);
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}
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if (pcibus) {
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/* Register network interfaces. */
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for (i = 0; i < nb_nics; i++) {
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/* There are no PCI NICs on the Bamboo board, but there are
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* PCI slots, so we can pick whatever default model we want. */
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pci_nic_init_nofail(&nd_table[i], "e1000", NULL);
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}
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}
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/* Load kernel. */
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if (kernel_filename) {
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success = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
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if (success < 0) {
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success = load_elf(kernel_filename, NULL, NULL, &elf_entry,
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&elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
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entry = elf_entry;
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loadaddr = elf_lowaddr;
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}
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/* XXX try again as binary */
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if (success < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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}
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/* Load initrd. */
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if (initrd_filename) {
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initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
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ram_size - RAMDISK_ADDR);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load ram disk '%s' at %x\n",
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initrd_filename, RAMDISK_ADDR);
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exit(1);
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}
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}
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/* If we're loading a kernel directly, we must load the device tree too. */
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if (kernel_filename) {
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if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR,
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initrd_size, kernel_cmdline) < 0) {
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fprintf(stderr, "couldn't load device tree\n");
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exit(1);
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}
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}
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if (kvm_enabled())
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kvmppc_init();
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}
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static QEMUMachine bamboo_machine = {
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.name = "bamboo",
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.desc = "bamboo",
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.init = bamboo_init,
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};
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static void bamboo_machine_init(void)
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{
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qemu_register_machine(&bamboo_machine);
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}
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machine_init(bamboo_machine_init);
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