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b0f26631bc
This lets the user specify the desired semantics. By default, the RTC will follow adjustments from the host's NTP client, and will remain in sync when the virtual machine is stopped. The previous behavior, which provides determinism with both icount and qtest, remains available with "-rtc clock=vm". pl031 supports migration, so we need to convert the time base from rtc_clock to vm_clock and back for backwards compatibility. (The rtc_clock may not be synchronized on the two machines, especially with savevm/loadvm, so the conversion is needed anyway. And since any time base will do, why not pick the one base that is backwards compatible). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
262 lines
6.9 KiB
C
262 lines
6.9 KiB
C
/*
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* ARM AMBA PrimeCell PL031 RTC
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*
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* Copyright (c) 2007 CodeSourcery
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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//#define DEBUG_PL031
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#ifdef DEBUG_PL031
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#define DPRINTF(fmt, ...) \
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do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#endif
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#define RTC_DR 0x00 /* Data read register */
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#define RTC_MR 0x04 /* Match register */
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#define RTC_LR 0x08 /* Data load register */
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#define RTC_CR 0x0c /* Control register */
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#define RTC_IMSC 0x10 /* Interrupt mask and set register */
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#define RTC_RIS 0x14 /* Raw interrupt status register */
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#define RTC_MIS 0x18 /* Masked interrupt status register */
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#define RTC_ICR 0x1c /* Interrupt clear register */
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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QEMUTimer *timer;
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qemu_irq irq;
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/* Needed to preserve the tick_count across migration, even if the
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* absolute value of the rtc_clock is different on the source and
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* destination.
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*/
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uint32_t tick_offset_vmstate;
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uint32_t tick_offset;
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uint32_t mr;
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uint32_t lr;
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uint32_t cr;
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uint32_t im;
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uint32_t is;
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} pl031_state;
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static const unsigned char pl031_id[] = {
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0x31, 0x10, 0x14, 0x00, /* Device ID */
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0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
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};
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static void pl031_update(pl031_state *s)
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{
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qemu_set_irq(s->irq, s->is & s->im);
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}
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static void pl031_interrupt(void * opaque)
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{
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pl031_state *s = (pl031_state *)opaque;
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s->is = 1;
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DPRINTF("Alarm raised\n");
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pl031_update(s);
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}
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static uint32_t pl031_get_count(pl031_state *s)
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{
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int64_t now = qemu_get_clock_ns(rtc_clock);
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return s->tick_offset + now / get_ticks_per_sec();
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}
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static void pl031_set_alarm(pl031_state *s)
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{
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uint32_t ticks;
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/* The timer wraps around. This subtraction also wraps in the same way,
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and gives correct results when alarm < now_ticks. */
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ticks = s->mr - pl031_get_count(s);
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DPRINTF("Alarm set in %ud ticks\n", ticks);
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if (ticks == 0) {
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qemu_del_timer(s->timer);
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pl031_interrupt(s);
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} else {
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int64_t now = qemu_get_clock_ns(rtc_clock);
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qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
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}
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}
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static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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pl031_state *s = (pl031_state *)opaque;
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if (offset >= 0xfe0 && offset < 0x1000)
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return pl031_id[(offset - 0xfe0) >> 2];
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switch (offset) {
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case RTC_DR:
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return pl031_get_count(s);
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case RTC_MR:
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return s->mr;
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case RTC_IMSC:
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return s->im;
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case RTC_RIS:
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return s->is;
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case RTC_LR:
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return s->lr;
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case RTC_CR:
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/* RTC is permanently enabled. */
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return 1;
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case RTC_MIS:
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return s->is & s->im;
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case RTC_ICR:
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fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
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(int)offset);
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break;
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default:
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hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
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break;
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}
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return 0;
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}
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static void pl031_write(void * opaque, target_phys_addr_t offset,
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uint64_t value, unsigned size)
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{
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pl031_state *s = (pl031_state *)opaque;
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switch (offset) {
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case RTC_LR:
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s->tick_offset += value - pl031_get_count(s);
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pl031_set_alarm(s);
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break;
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case RTC_MR:
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s->mr = value;
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pl031_set_alarm(s);
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break;
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case RTC_IMSC:
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s->im = value & 1;
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DPRINTF("Interrupt mask %d\n", s->im);
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pl031_update(s);
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break;
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case RTC_ICR:
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/* The PL031 documentation (DDI0224B) states that the interrupt is
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cleared when bit 0 of the written value is set. However the
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arm926e documentation (DDI0287B) states that the interrupt is
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cleared when any value is written. */
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DPRINTF("Interrupt cleared");
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s->is = 0;
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pl031_update(s);
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break;
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case RTC_CR:
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/* Written value is ignored. */
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break;
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case RTC_DR:
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case RTC_MIS:
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case RTC_RIS:
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fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
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(int)offset);
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break;
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default:
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hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
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break;
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}
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}
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static const MemoryRegionOps pl031_ops = {
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.read = pl031_read,
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.write = pl031_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pl031_init(SysBusDevice *dev)
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{
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pl031_state *s = FROM_SYSBUS(pl031_state, dev);
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struct tm tm;
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memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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qemu_get_timedate(&tm, 0);
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s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
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s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
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return 0;
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}
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static void pl031_pre_save(void *opaque)
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{
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pl031_state *s = opaque;
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/* tick_offset is base_time - rtc_clock base time. Instead, we want to
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* store the base time relative to the vm_clock for backwards-compatibility. */
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int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
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s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
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}
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static int pl031_post_load(void *opaque, int version_id)
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{
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pl031_state *s = opaque;
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int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
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s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
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pl031_set_alarm(s);
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return 0;
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}
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static const VMStateDescription vmstate_pl031 = {
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.name = "pl031",
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.version_id = 1,
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.minimum_version_id = 1,
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.pre_save = pl031_pre_save,
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.post_load = pl031_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
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VMSTATE_UINT32(mr, pl031_state),
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VMSTATE_UINT32(lr, pl031_state),
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VMSTATE_UINT32(cr, pl031_state),
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VMSTATE_UINT32(im, pl031_state),
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VMSTATE_UINT32(is, pl031_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pl031_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = pl031_init;
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dc->no_user = 1;
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dc->vmsd = &vmstate_pl031;
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}
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static TypeInfo pl031_info = {
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.name = "pl031",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(pl031_state),
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.class_init = pl031_class_init,
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};
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static void pl031_register_types(void)
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{
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type_register_static(&pl031_info);
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}
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type_init(pl031_register_types)
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