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83f7d43a9e
Replace device_init() with generalized type_init(). While at it, unify naming convention: type_init([$prefix_]register_types) Also, type_init() is a function, so add preceding blank line where necessary and don't put a semicolon after the closing brace. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Anthony Liguori <anthony@codemonkey.ws> Cc: malc <av1474@comtv.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
345 lines
8.3 KiB
C
345 lines
8.3 KiB
C
/*
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* QEMU model of the Milkymist System Controller.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.milkymist.org/socdoc/ac97.pdf
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*/
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#include "hw.h"
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#include "sysbus.h"
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#include "trace.h"
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#include "audio/audio.h"
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#include "qemu-error.h"
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enum {
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R_AC97_CTRL = 0,
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R_AC97_ADDR,
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R_AC97_DATAOUT,
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R_AC97_DATAIN,
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R_D_CTRL,
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R_D_ADDR,
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R_D_REMAINING,
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R_RESERVED,
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R_U_CTRL,
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R_U_ADDR,
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R_U_REMAINING,
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R_MAX
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};
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enum {
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AC97_CTRL_RQEN = (1<<0),
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AC97_CTRL_WRITE = (1<<1),
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};
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enum {
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CTRL_EN = (1<<0),
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};
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struct MilkymistAC97State {
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SysBusDevice busdev;
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MemoryRegion regs_region;
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QEMUSoundCard card;
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SWVoiceIn *voice_in;
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SWVoiceOut *voice_out;
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uint32_t regs[R_MAX];
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qemu_irq crrequest_irq;
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qemu_irq crreply_irq;
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qemu_irq dmar_irq;
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qemu_irq dmaw_irq;
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};
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typedef struct MilkymistAC97State MilkymistAC97State;
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static void update_voices(MilkymistAC97State *s)
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{
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if (s->regs[R_D_CTRL] & CTRL_EN) {
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AUD_set_active_out(s->voice_out, 1);
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} else {
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AUD_set_active_out(s->voice_out, 0);
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}
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if (s->regs[R_U_CTRL] & CTRL_EN) {
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AUD_set_active_in(s->voice_in, 1);
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} else {
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AUD_set_active_in(s->voice_in, 0);
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}
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}
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static uint64_t ac97_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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MilkymistAC97State *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_AC97_CTRL:
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case R_AC97_ADDR:
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case R_AC97_DATAOUT:
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case R_AC97_DATAIN:
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case R_D_CTRL:
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case R_D_ADDR:
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case R_D_REMAINING:
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case R_U_CTRL:
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case R_U_ADDR:
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case R_U_REMAINING:
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r = s->regs[addr];
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break;
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default:
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error_report("milkymist_ac97: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_milkymist_ac97_memory_read(addr << 2, r);
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return r;
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}
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static void ac97_write(void *opaque, target_phys_addr_t addr, uint64_t value,
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unsigned size)
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{
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MilkymistAC97State *s = opaque;
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trace_milkymist_ac97_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_AC97_CTRL:
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/* always raise an IRQ according to the direction */
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if (value & AC97_CTRL_RQEN) {
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if (value & AC97_CTRL_WRITE) {
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trace_milkymist_ac97_pulse_irq_crrequest();
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qemu_irq_pulse(s->crrequest_irq);
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} else {
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trace_milkymist_ac97_pulse_irq_crreply();
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qemu_irq_pulse(s->crreply_irq);
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}
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}
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/* RQEN is self clearing */
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s->regs[addr] = value & ~AC97_CTRL_RQEN;
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break;
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case R_D_CTRL:
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case R_U_CTRL:
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s->regs[addr] = value;
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update_voices(s);
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break;
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case R_AC97_ADDR:
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case R_AC97_DATAOUT:
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case R_AC97_DATAIN:
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case R_D_ADDR:
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case R_D_REMAINING:
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case R_U_ADDR:
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case R_U_REMAINING:
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s->regs[addr] = value;
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break;
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default:
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error_report("milkymist_ac97: write access to unknown register 0x"
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TARGET_FMT_plx, addr);
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break;
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}
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}
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static const MemoryRegionOps ac97_mmio_ops = {
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.read = ac97_read,
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.write = ac97_write,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ac97_in_cb(void *opaque, int avail_b)
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{
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MilkymistAC97State *s = opaque;
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uint8_t buf[4096];
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uint32_t remaining = s->regs[R_U_REMAINING];
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int temp = audio_MIN(remaining, avail_b);
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uint32_t addr = s->regs[R_U_ADDR];
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int transferred = 0;
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trace_milkymist_ac97_in_cb(avail_b, remaining);
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/* prevent from raising an IRQ */
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if (temp == 0) {
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return;
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}
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while (temp) {
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int acquired, to_copy;
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to_copy = audio_MIN(temp, sizeof(buf));
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acquired = AUD_read(s->voice_in, buf, to_copy);
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if (!acquired) {
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break;
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}
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cpu_physical_memory_write(addr, buf, acquired);
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temp -= acquired;
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addr += acquired;
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transferred += acquired;
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}
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trace_milkymist_ac97_in_cb_transferred(transferred);
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s->regs[R_U_ADDR] = addr;
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s->regs[R_U_REMAINING] -= transferred;
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if ((s->regs[R_U_CTRL] & CTRL_EN) && (s->regs[R_U_REMAINING] == 0)) {
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trace_milkymist_ac97_pulse_irq_dmaw();
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qemu_irq_pulse(s->dmaw_irq);
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}
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}
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static void ac97_out_cb(void *opaque, int free_b)
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{
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MilkymistAC97State *s = opaque;
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uint8_t buf[4096];
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uint32_t remaining = s->regs[R_D_REMAINING];
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int temp = audio_MIN(remaining, free_b);
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uint32_t addr = s->regs[R_D_ADDR];
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int transferred = 0;
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trace_milkymist_ac97_out_cb(free_b, remaining);
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/* prevent from raising an IRQ */
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if (temp == 0) {
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return;
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}
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while (temp) {
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int copied, to_copy;
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to_copy = audio_MIN(temp, sizeof(buf));
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cpu_physical_memory_read(addr, buf, to_copy);
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copied = AUD_write(s->voice_out, buf, to_copy);
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if (!copied) {
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break;
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}
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temp -= copied;
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addr += copied;
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transferred += copied;
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}
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trace_milkymist_ac97_out_cb_transferred(transferred);
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s->regs[R_D_ADDR] = addr;
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s->regs[R_D_REMAINING] -= transferred;
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if ((s->regs[R_D_CTRL] & CTRL_EN) && (s->regs[R_D_REMAINING] == 0)) {
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trace_milkymist_ac97_pulse_irq_dmar();
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qemu_irq_pulse(s->dmar_irq);
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}
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}
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static void milkymist_ac97_reset(DeviceState *d)
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{
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MilkymistAC97State *s = container_of(d, MilkymistAC97State, busdev.qdev);
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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AUD_set_active_in(s->voice_in, 0);
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AUD_set_active_out(s->voice_out, 0);
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}
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static int ac97_post_load(void *opaque, int version_id)
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{
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MilkymistAC97State *s = opaque;
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update_voices(s);
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return 0;
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}
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static int milkymist_ac97_init(SysBusDevice *dev)
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{
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MilkymistAC97State *s = FROM_SYSBUS(typeof(*s), dev);
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struct audsettings as;
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sysbus_init_irq(dev, &s->crrequest_irq);
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sysbus_init_irq(dev, &s->crreply_irq);
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sysbus_init_irq(dev, &s->dmar_irq);
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sysbus_init_irq(dev, &s->dmaw_irq);
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AUD_register_card("Milkymist AC'97", &s->card);
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as.freq = 48000;
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as.nchannels = 2;
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as.fmt = AUD_FMT_S16;
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as.endianness = 1;
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s->voice_in = AUD_open_in(&s->card, s->voice_in,
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"mm_ac97.in", s, ac97_in_cb, &as);
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s->voice_out = AUD_open_out(&s->card, s->voice_out,
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"mm_ac97.out", s, ac97_out_cb, &as);
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memory_region_init_io(&s->regs_region, &ac97_mmio_ops, s,
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"milkymist-ac97", R_MAX * 4);
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sysbus_init_mmio(dev, &s->regs_region);
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return 0;
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}
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static const VMStateDescription vmstate_milkymist_ac97 = {
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.name = "milkymist-ac97",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = ac97_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, MilkymistAC97State, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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static void milkymist_ac97_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = milkymist_ac97_init;
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dc->reset = milkymist_ac97_reset;
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dc->vmsd = &vmstate_milkymist_ac97;
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}
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static TypeInfo milkymist_ac97_info = {
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.name = "milkymist-ac97",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MilkymistAC97State),
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.class_init = milkymist_ac97_class_init,
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};
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static void milkymist_ac97_register_types(void)
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{
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type_register_static(&milkymist_ac97_info);
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}
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type_init(milkymist_ac97_register_types)
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