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4e27e819be
This adds visitor interfaces for fixed-width integers types. Implementing these in visitors is optional, otherwise we fall back to visit_type_int() (int64_t) with some additional bounds checking to avoid integer overflows for cases where the value fetched exceeds the bounds of our target C type. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [LE: exclude negative values in uint*_t Visitor interfaces] Signed-off-by: Laszlo Ersek <lersek@redhat.com> [AF: Merged fix by Laszlo] Signed-off-by: Andreas Färber <afaerber@suse.de>
716 lines
22 KiB
C
716 lines
22 KiB
C
/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "sysemu.h"
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#include "mc146818rtc.h"
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#ifdef TARGET_I386
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#include "apic.h"
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#endif
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//#define DEBUG_CMOS
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//#define DEBUG_COALESCED
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#ifdef DEBUG_CMOS
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# define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define CMOS_DPRINTF(format, ...) do { } while (0)
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#endif
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#ifdef DEBUG_COALESCED
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# define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__)
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#else
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# define DPRINTF_C(format, ...) do { } while (0)
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#endif
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#define RTC_REINJECT_ON_ACK_COUNT 20
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typedef struct RTCState {
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ISADevice dev;
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MemoryRegion io;
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uint8_t cmos_data[128];
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uint8_t cmos_index;
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struct tm current_tm;
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int32_t base_year;
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qemu_irq irq;
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qemu_irq sqw_irq;
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer;
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int64_t next_periodic_time;
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/* second update */
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int64_t next_second_time;
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uint16_t irq_reinject_on_ack_count;
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uint32_t irq_coalesced;
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uint32_t period;
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QEMUTimer *coalesced_timer;
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QEMUTimer *second_timer;
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QEMUTimer *second_timer2;
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Notifier clock_reset_notifier;
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LostTickPolicy lost_tick_policy;
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Notifier suspend_notifier;
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} RTCState;
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static void rtc_set_time(RTCState *s);
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static void rtc_copy_date(RTCState *s);
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s)
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{
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if (s->irq_coalesced == 0) {
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qemu_del_timer(s->coalesced_timer);
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1;
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int64_t next_clock = qemu_get_clock_ns(rtc_clock) +
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock);
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}
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}
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static void rtc_coalesced_timer(void *opaque)
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{
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RTCState *s = opaque;
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if (s->irq_coalesced != 0) {
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apic_reset_irq_delivered();
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s->cmos_data[RTC_REG_C] |= 0xc0;
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DPRINTF_C("cmos: injecting from timer\n");
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qemu_irq_raise(s->irq);
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--;
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DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
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s->irq_coalesced);
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}
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}
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rtc_coalesced_timer_update(s);
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}
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#endif
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static void rtc_timer_update(RTCState *s, int64_t current_time)
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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if (period_code != 0
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&& ((s->cmos_data[RTC_REG_B] & REG_B_PIE)
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2)
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1);
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#ifdef TARGET_I386
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if (period != s->period) {
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s->irq_coalesced = (s->irq_coalesced * s->period) / period;
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DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
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}
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s->period = period;
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time =
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer);
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}
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}
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static void rtc_periodic_timer(void *opaque)
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{
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RTCState *s = opaque;
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rtc_timer_update(s, s->next_periodic_time);
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s->cmos_data[RTC_REG_C] |= REG_C_PF;
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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#ifdef TARGET_I386
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if (s->lost_tick_policy == LOST_TICK_SLEW) {
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered();
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qemu_irq_raise(s->irq);
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++;
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rtc_coalesced_timer_update(s);
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DPRINTF_C("cmos: coalesced irqs increased to %d\n",
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s->irq_coalesced);
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}
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} else
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#endif
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qemu_irq_raise(s->irq);
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}
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq);
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}
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}
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
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{
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RTCState *s = opaque;
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if ((addr & 1) == 0) {
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s->cmos_index = data & 0x7f;
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} else {
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CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data);
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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s->cmos_data[s->cmos_index] = data;
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data;
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s);
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}
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP);
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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data &= ~REG_B_UIE;
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s);
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}
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}
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if (((s->cmos_data[RTC_REG_B] ^ data) & (REG_B_DM | REG_B_24H)) &&
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!(data & REG_B_SET)) {
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/* If the time format has changed and not in set mode,
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update the registers immediately. */
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s->cmos_data[RTC_REG_B] = data;
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rtc_copy_date(s);
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} else {
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s->cmos_data[RTC_REG_B] = data;
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}
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rtc_timer_update(s, qemu_get_clock_ns(rtc_clock));
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data;
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break;
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}
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}
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}
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static inline int rtc_to_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10);
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}
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}
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static inline int rtc_from_bcd(RTCState *s, int a)
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f);
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}
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}
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static void rtc_set_time(RTCState *s)
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{
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struct tm *tm = &s->current_tm;
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tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
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tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
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tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
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tm->tm_hour %= 12;
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if (s->cmos_data[RTC_HOURS] & 0x80) {
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tm->tm_hour += 12;
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}
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}
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tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
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tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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rtc_change_mon_event(tm);
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}
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static void rtc_copy_date(RTCState *s)
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{
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const struct tm *tm = &s->current_tm;
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int year;
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s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
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s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
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if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
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} else {
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/* 12 hour format */
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int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
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if (tm->tm_hour >= 12)
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s->cmos_data[RTC_HOURS] |= 0x80;
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}
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s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
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s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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if (year < 0)
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year += 100;
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s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
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}
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/* month is between 0 and 11. */
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static int get_days_in_month(int month, int year)
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{
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static const int days_tab[12] = {
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
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};
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int d;
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if ((unsigned )month >= 12)
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return 31;
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d = days_tab[month];
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if (month == 1) {
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if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
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d++;
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}
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return d;
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}
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/* update 'tm' to the next second */
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static void rtc_next_second(struct tm *tm)
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{
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int days_in_month;
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tm->tm_sec++;
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if ((unsigned)tm->tm_sec >= 60) {
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tm->tm_sec = 0;
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tm->tm_min++;
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if ((unsigned)tm->tm_min >= 60) {
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tm->tm_min = 0;
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tm->tm_hour++;
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if ((unsigned)tm->tm_hour >= 24) {
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tm->tm_hour = 0;
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/* next day */
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tm->tm_wday++;
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if ((unsigned)tm->tm_wday >= 7)
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tm->tm_wday = 0;
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days_in_month = get_days_in_month(tm->tm_mon,
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tm->tm_year + 1900);
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tm->tm_mday++;
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if (tm->tm_mday < 1) {
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tm->tm_mday = 1;
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} else if (tm->tm_mday > days_in_month) {
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tm->tm_mday = 1;
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tm->tm_mon++;
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if (tm->tm_mon >= 12) {
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tm->tm_mon = 0;
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tm->tm_year++;
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}
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}
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}
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}
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}
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}
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static void rtc_update_second(void *opaque)
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{
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RTCState *s = opaque;
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int64_t delay;
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/* if the oscillator is not in normal operation, we do not update */
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if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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} else {
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rtc_next_second(&s->current_tm);
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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/* update in progress bit */
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s->cmos_data[RTC_REG_A] |= REG_A_UIP;
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}
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/* should be 244 us = 8 / 32768 seconds, but currently the
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timers do not have the necessary resolution. */
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delay = (get_ticks_per_sec() * 1) / 100;
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if (delay < 1)
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delay = 1;
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qemu_mod_timer(s->second_timer2,
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s->next_second_time + delay);
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}
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}
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static void rtc_update_second2(void *opaque)
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{
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RTCState *s = opaque;
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_copy_date(s);
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}
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/* check alarm */
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if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]) == s->current_tm.tm_sec) &&
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((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]) == s->current_tm.tm_min) &&
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((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
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rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]) == s->current_tm.tm_hour)) {
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s->cmos_data[RTC_REG_C] |= REG_C_AF;
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if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
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qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
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qemu_irq_raise(s->irq);
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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}
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}
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/* update ended interrupt */
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s->cmos_data[RTC_REG_C] |= REG_C_UF;
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if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
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s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
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qemu_irq_raise(s->irq);
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}
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/* clear update in progress bit */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
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s->next_second_time += get_ticks_per_sec();
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qemu_mod_timer(s->second_timer, s->next_second_time);
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}
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static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
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{
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RTCState *s = opaque;
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int ret;
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if ((addr & 1) == 0) {
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return 0xff;
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} else {
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switch(s->cmos_index) {
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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ret = s->cmos_data[s->cmos_index];
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break;
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|
case RTC_REG_A:
|
|
ret = s->cmos_data[s->cmos_index];
|
|
break;
|
|
case RTC_REG_C:
|
|
ret = s->cmos_data[s->cmos_index];
|
|
qemu_irq_lower(s->irq);
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
#ifdef TARGET_I386
|
|
if(s->irq_coalesced &&
|
|
(s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
|
|
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
|
|
s->irq_reinject_on_ack_count++;
|
|
s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
|
|
apic_reset_irq_delivered();
|
|
DPRINTF_C("cmos: injecting on ack\n");
|
|
qemu_irq_raise(s->irq);
|
|
if (apic_get_irq_delivered()) {
|
|
s->irq_coalesced--;
|
|
DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
|
|
s->irq_coalesced);
|
|
}
|
|
}
|
|
#endif
|
|
break;
|
|
default:
|
|
ret = s->cmos_data[s->cmos_index];
|
|
break;
|
|
}
|
|
CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
|
|
s->cmos_index, ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
void rtc_set_memory(ISADevice *dev, int addr, int val)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
if (addr >= 0 && addr <= 127)
|
|
s->cmos_data[addr] = val;
|
|
}
|
|
|
|
void rtc_set_date(ISADevice *dev, const struct tm *tm)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
s->current_tm = *tm;
|
|
rtc_copy_date(s);
|
|
}
|
|
|
|
/* PC cmos mappings */
|
|
#define REG_IBM_CENTURY_BYTE 0x32
|
|
#define REG_IBM_PS2_CENTURY_BYTE 0x37
|
|
|
|
static void rtc_set_date_from_host(ISADevice *dev)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
struct tm tm;
|
|
int val;
|
|
|
|
/* set the CMOS date */
|
|
qemu_get_timedate(&tm, 0);
|
|
rtc_set_date(dev, &tm);
|
|
|
|
val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
|
|
rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
|
|
rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
|
|
}
|
|
|
|
static int rtc_post_load(void *opaque, int version_id)
|
|
{
|
|
#ifdef TARGET_I386
|
|
RTCState *s = opaque;
|
|
|
|
if (version_id >= 2) {
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
rtc_coalesced_timer_update(s);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_rtc = {
|
|
.name = "mc146818rtc",
|
|
.version_id = 2,
|
|
.minimum_version_id = 1,
|
|
.minimum_version_id_old = 1,
|
|
.post_load = rtc_post_load,
|
|
.fields = (VMStateField []) {
|
|
VMSTATE_BUFFER(cmos_data, RTCState),
|
|
VMSTATE_UINT8(cmos_index, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_sec, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_min, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_hour, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_wday, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_mday, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_mon, RTCState),
|
|
VMSTATE_INT32(current_tm.tm_year, RTCState),
|
|
VMSTATE_TIMER(periodic_timer, RTCState),
|
|
VMSTATE_INT64(next_periodic_time, RTCState),
|
|
VMSTATE_INT64(next_second_time, RTCState),
|
|
VMSTATE_TIMER(second_timer, RTCState),
|
|
VMSTATE_TIMER(second_timer2, RTCState),
|
|
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
|
VMSTATE_UINT32_V(period, RTCState, 2),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void rtc_notify_clock_reset(Notifier *notifier, void *data)
|
|
{
|
|
RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
|
|
int64_t now = *(int64_t *)data;
|
|
|
|
rtc_set_date_from_host(&s->dev);
|
|
s->next_second_time = now + (get_ticks_per_sec() * 99) / 100;
|
|
qemu_mod_timer(s->second_timer2, s->next_second_time);
|
|
rtc_timer_update(s, now);
|
|
#ifdef TARGET_I386
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
rtc_coalesced_timer_update(s);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
|
|
BIOS will read it and start S3 resume at POST Entry */
|
|
static void rtc_notify_suspend(Notifier *notifier, void *data)
|
|
{
|
|
RTCState *s = container_of(notifier, RTCState, suspend_notifier);
|
|
rtc_set_memory(&s->dev, 0xF, 0xFE);
|
|
}
|
|
|
|
static void rtc_reset(void *opaque)
|
|
{
|
|
RTCState *s = opaque;
|
|
|
|
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
|
|
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
#ifdef TARGET_I386
|
|
if (s->lost_tick_policy == LOST_TICK_SLEW) {
|
|
s->irq_coalesced = 0;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static const MemoryRegionPortio cmos_portio[] = {
|
|
{0, 2, 1, .read = cmos_ioport_read, .write = cmos_ioport_write },
|
|
PORTIO_END_OF_LIST(),
|
|
};
|
|
|
|
static const MemoryRegionOps cmos_ops = {
|
|
.old_portio = cmos_portio
|
|
};
|
|
|
|
static void rtc_get_date(Object *obj, Visitor *v, void *opaque,
|
|
const char *name, Error **errp)
|
|
{
|
|
ISADevice *isa = ISA_DEVICE(obj);
|
|
RTCState *s = DO_UPCAST(RTCState, dev, isa);
|
|
|
|
visit_start_struct(v, NULL, "struct tm", name, 0, errp);
|
|
visit_type_int32(v, &s->current_tm.tm_year, "tm_year", errp);
|
|
visit_type_int32(v, &s->current_tm.tm_mon, "tm_mon", errp);
|
|
visit_type_int32(v, &s->current_tm.tm_mday, "tm_mday", errp);
|
|
visit_type_int32(v, &s->current_tm.tm_hour, "tm_hour", errp);
|
|
visit_type_int32(v, &s->current_tm.tm_min, "tm_min", errp);
|
|
visit_type_int32(v, &s->current_tm.tm_sec, "tm_sec", errp);
|
|
visit_end_struct(v, errp);
|
|
}
|
|
|
|
static int rtc_initfn(ISADevice *dev)
|
|
{
|
|
RTCState *s = DO_UPCAST(RTCState, dev, dev);
|
|
int base = 0x70;
|
|
|
|
s->cmos_data[RTC_REG_A] = 0x26;
|
|
s->cmos_data[RTC_REG_B] = 0x02;
|
|
s->cmos_data[RTC_REG_C] = 0x00;
|
|
s->cmos_data[RTC_REG_D] = 0x80;
|
|
|
|
rtc_set_date_from_host(dev);
|
|
|
|
#ifdef TARGET_I386
|
|
switch (s->lost_tick_policy) {
|
|
case LOST_TICK_SLEW:
|
|
s->coalesced_timer =
|
|
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
|
|
break;
|
|
case LOST_TICK_DISCARD:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
#endif
|
|
|
|
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
|
|
s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
|
|
s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
|
|
|
|
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
|
|
qemu_register_clock_reset_notifier(rtc_clock, &s->clock_reset_notifier);
|
|
|
|
s->suspend_notifier.notify = rtc_notify_suspend;
|
|
qemu_register_suspend_notifier(&s->suspend_notifier);
|
|
|
|
s->next_second_time =
|
|
qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
|
|
qemu_mod_timer(s->second_timer2, s->next_second_time);
|
|
|
|
memory_region_init_io(&s->io, &cmos_ops, s, "rtc", 2);
|
|
isa_register_ioport(dev, &s->io, base);
|
|
|
|
qdev_set_legacy_instance_id(&dev->qdev, base, 2);
|
|
qemu_register_reset(rtc_reset, s);
|
|
|
|
object_property_add(OBJECT(s), "date", "struct tm",
|
|
rtc_get_date, NULL, NULL, s, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
|
|
{
|
|
ISADevice *dev;
|
|
RTCState *s;
|
|
|
|
dev = isa_create(bus, "mc146818rtc");
|
|
s = DO_UPCAST(RTCState, dev, dev);
|
|
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
|
qdev_init_nofail(&dev->qdev);
|
|
if (intercept_irq) {
|
|
s->irq = intercept_irq;
|
|
} else {
|
|
isa_init_irq(dev, &s->irq, RTC_ISA_IRQ);
|
|
}
|
|
return dev;
|
|
}
|
|
|
|
static Property mc146818rtc_properties[] = {
|
|
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
|
|
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
|
|
lost_tick_policy, LOST_TICK_DISCARD),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void rtc_class_initfn(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
|
|
ic->init = rtc_initfn;
|
|
dc->no_user = 1;
|
|
dc->vmsd = &vmstate_rtc;
|
|
dc->props = mc146818rtc_properties;
|
|
}
|
|
|
|
static TypeInfo mc146818rtc_info = {
|
|
.name = "mc146818rtc",
|
|
.parent = TYPE_ISA_DEVICE,
|
|
.instance_size = sizeof(RTCState),
|
|
.class_init = rtc_class_initfn,
|
|
};
|
|
|
|
static void mc146818rtc_register_types(void)
|
|
{
|
|
type_register_static(&mc146818rtc_info);
|
|
}
|
|
|
|
type_init(mc146818rtc_register_types)
|