mirror of
https://github.com/qemu/qemu.git
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7267c0947d
qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
179 lines
4.9 KiB
C
179 lines
4.9 KiB
C
/*
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* LatticeMico32 hwsetup helper functions.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* These are helper functions for creating the hardware description blob used
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* in the Theobroma's uClinux port.
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*/
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#ifndef QEMU_HW_LM32_HWSETUP_H
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#define QEMU_HW_LM32_HWSETUP_H
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#include "qemu-common.h"
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#include "loader.h"
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typedef struct {
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void *data;
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void *ptr;
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} HWSetup;
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enum hwsetup_tag {
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HWSETUP_TAG_EOL = 0,
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HWSETUP_TAG_CPU = 1,
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HWSETUP_TAG_ASRAM = 2,
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HWSETUP_TAG_FLASH = 3,
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HWSETUP_TAG_SDRAM = 4,
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HWSETUP_TAG_OCM = 5,
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HWSETUP_TAG_DDR_SDRAM = 6,
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HWSETUP_TAG_DDR2_SDRAM = 7,
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HWSETUP_TAG_TIMER = 8,
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HWSETUP_TAG_UART = 9,
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HWSETUP_TAG_GPIO = 10,
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HWSETUP_TAG_TRISPEEDMAC = 11,
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HWSETUP_TAG_I2CM = 12,
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HWSETUP_TAG_LEDS = 13,
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HWSETUP_TAG_7SEG = 14,
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HWSETUP_TAG_SPI_S = 15,
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HWSETUP_TAG_SPI_M = 16,
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};
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static inline HWSetup *hwsetup_init(void)
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{
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HWSetup *hw;
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hw = g_malloc(sizeof(HWSetup));
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hw->data = g_malloc0(TARGET_PAGE_SIZE);
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hw->ptr = hw->data;
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return hw;
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}
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static inline void hwsetup_free(HWSetup *hw)
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{
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g_free(hw->data);
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g_free(hw);
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}
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static inline void hwsetup_create_rom(HWSetup *hw,
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target_phys_addr_t base)
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{
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rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
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}
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static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
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{
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stb_p(hw->ptr, u);
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hw->ptr += 1;
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}
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static inline void hwsetup_add_u32(HWSetup *hw, uint32_t u)
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{
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stl_p(hw->ptr, u);
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hw->ptr += 4;
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}
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static inline void hwsetup_add_tag(HWSetup *hw, enum hwsetup_tag t)
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{
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stl_p(hw->ptr, t);
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hw->ptr += 4;
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}
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static inline void hwsetup_add_str(HWSetup *hw, const char *str)
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{
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strncpy(hw->ptr, str, 31); /* make sure last byte is zero */
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hw->ptr += 32;
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}
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static inline void hwsetup_add_trailer(HWSetup *hw)
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{
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hwsetup_add_u32(hw, 8); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_EOL);
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}
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static inline void hwsetup_add_cpu(HWSetup *hw,
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const char *name, uint32_t frequency)
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{
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hwsetup_add_u32(hw, 44); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_CPU);
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hwsetup_add_str(hw, name);
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hwsetup_add_u32(hw, frequency);
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}
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static inline void hwsetup_add_flash(HWSetup *hw,
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const char *name, uint32_t base, uint32_t size)
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{
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hwsetup_add_u32(hw, 52); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_FLASH);
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hwsetup_add_str(hw, name);
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hwsetup_add_u32(hw, base);
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hwsetup_add_u32(hw, size);
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hwsetup_add_u8(hw, 8); /* read latency */
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hwsetup_add_u8(hw, 8); /* write latency */
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hwsetup_add_u8(hw, 25); /* address width */
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hwsetup_add_u8(hw, 32); /* data width */
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}
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static inline void hwsetup_add_ddr_sdram(HWSetup *hw,
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const char *name, uint32_t base, uint32_t size)
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{
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hwsetup_add_u32(hw, 48); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_DDR_SDRAM);
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hwsetup_add_str(hw, name);
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hwsetup_add_u32(hw, base);
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hwsetup_add_u32(hw, size);
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}
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static inline void hwsetup_add_timer(HWSetup *hw,
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const char *name, uint32_t base, uint32_t irq)
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{
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hwsetup_add_u32(hw, 56); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_TIMER);
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hwsetup_add_str(hw, name);
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hwsetup_add_u32(hw, base);
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hwsetup_add_u8(hw, 1); /* wr_tickcount */
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hwsetup_add_u8(hw, 1); /* rd_tickcount */
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hwsetup_add_u8(hw, 1); /* start_stop_control */
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hwsetup_add_u8(hw, 32); /* counter_width */
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hwsetup_add_u32(hw, 20); /* reload_ticks */
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hwsetup_add_u8(hw, irq);
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hwsetup_add_u8(hw, 0); /* padding */
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hwsetup_add_u8(hw, 0); /* padding */
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hwsetup_add_u8(hw, 0); /* padding */
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}
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static inline void hwsetup_add_uart(HWSetup *hw,
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const char *name, uint32_t base, uint32_t irq)
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{
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hwsetup_add_u32(hw, 56); /* size */
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hwsetup_add_tag(hw, HWSETUP_TAG_UART);
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hwsetup_add_str(hw, name);
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hwsetup_add_u32(hw, base);
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hwsetup_add_u32(hw, 115200); /* baudrate */
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hwsetup_add_u8(hw, 8); /* databits */
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hwsetup_add_u8(hw, 1); /* stopbits */
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hwsetup_add_u8(hw, 1); /* use_interrupt */
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hwsetup_add_u8(hw, 1); /* block_on_transmit */
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hwsetup_add_u8(hw, 1); /* block_on_receive */
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hwsetup_add_u8(hw, 4); /* rx_buffer_size */
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hwsetup_add_u8(hw, 4); /* tx_buffer_size */
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hwsetup_add_u8(hw, irq);
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}
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#endif /* QEMU_HW_LM32_HWSETUP_H */
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