mirror of
https://github.com/qemu/qemu.git
synced 2024-12-06 02:03:38 +08:00
1e8cae4dfe
Rearrange the GIC and NVIC so both are straightforward subclasses of a common class, rather than having the NVIC source file textually include arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
137 lines
5.1 KiB
C
137 lines
5.1 KiB
C
/*
|
|
* ARM GIC support - internal interfaces
|
|
*
|
|
* Copyright (c) 2012 Linaro Limited
|
|
* Written by Peter Maydell
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation, either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License along
|
|
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
|
*/
|
|
|
|
#ifndef QEMU_ARM_GIC_INTERNAL_H
|
|
#define QEMU_ARM_GIC_INTERNAL_H
|
|
|
|
#include "sysbus.h"
|
|
|
|
/* Maximum number of possible interrupts, determined by the GIC architecture */
|
|
#define GIC_MAXIRQ 1020
|
|
/* First 32 are private to each CPU (SGIs and PPIs). */
|
|
#define GIC_INTERNAL 32
|
|
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
|
|
#define NCPU 8
|
|
|
|
#define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1)))
|
|
|
|
/* The NVIC has 16 internal vectors. However these are not exposed
|
|
through the normal GIC interface. */
|
|
#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
|
|
|
|
#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
|
|
#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
|
|
#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
|
|
#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
|
|
#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
|
|
#define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
|
|
#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
|
|
#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
|
|
#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
|
|
#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
|
|
#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
|
|
#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
|
|
#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
|
|
#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
|
|
#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
|
|
#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
|
|
#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
|
|
#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
|
|
#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
|
|
s->priority1[irq][cpu] : \
|
|
s->priority2[(irq) - GIC_INTERNAL])
|
|
#define GIC_TARGET(irq) s->irq_target[irq]
|
|
|
|
typedef struct gic_irq_state {
|
|
/* The enable bits are only banked for per-cpu interrupts. */
|
|
unsigned enabled:NCPU;
|
|
unsigned pending:NCPU;
|
|
unsigned active:NCPU;
|
|
unsigned level:NCPU;
|
|
unsigned model:1; /* 0 = N:N, 1 = 1:N */
|
|
unsigned trigger:1; /* nonzero = edge triggered. */
|
|
} gic_irq_state;
|
|
|
|
typedef struct gic_state {
|
|
SysBusDevice busdev;
|
|
qemu_irq parent_irq[NCPU];
|
|
int enabled;
|
|
int cpu_enabled[NCPU];
|
|
|
|
gic_irq_state irq_state[GIC_MAXIRQ];
|
|
int irq_target[GIC_MAXIRQ];
|
|
int priority1[GIC_INTERNAL][NCPU];
|
|
int priority2[GIC_MAXIRQ - GIC_INTERNAL];
|
|
int last_active[GIC_MAXIRQ][NCPU];
|
|
|
|
int priority_mask[NCPU];
|
|
int running_irq[NCPU];
|
|
int running_priority[NCPU];
|
|
int current_pending[NCPU];
|
|
|
|
uint32_t num_cpu;
|
|
|
|
MemoryRegion iomem; /* Distributor */
|
|
/* This is just so we can have an opaque pointer which identifies
|
|
* both this GIC and which CPU interface we should be accessing.
|
|
*/
|
|
struct gic_state *backref[NCPU];
|
|
MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */
|
|
uint32_t num_irq;
|
|
uint32_t revision;
|
|
} gic_state;
|
|
|
|
/* The special cases for the revision property: */
|
|
#define REV_11MPCORE 0
|
|
#define REV_NVIC 0xffffffff
|
|
|
|
void gic_set_pending_private(gic_state *s, int cpu, int irq);
|
|
uint32_t gic_acknowledge_irq(gic_state *s, int cpu);
|
|
void gic_complete_irq(gic_state *s, int cpu, int irq);
|
|
void gic_update(gic_state *s);
|
|
void gic_init_irqs_and_distributor(gic_state *s, int num_irq);
|
|
|
|
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
|
|
#define ARM_GIC_COMMON(obj) \
|
|
OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC_COMMON)
|
|
#define ARM_GIC_COMMON_CLASS(klass) \
|
|
OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON)
|
|
#define ARM_GIC_COMMON_GET_CLASS(obj) \
|
|
OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON)
|
|
|
|
typedef struct ARMGICCommonClass {
|
|
SysBusDeviceClass parent_class;
|
|
} ARMGICCommonClass;
|
|
|
|
#define TYPE_ARM_GIC "arm_gic"
|
|
#define ARM_GIC(obj) \
|
|
OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC)
|
|
#define ARM_GIC_CLASS(klass) \
|
|
OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC)
|
|
#define ARM_GIC_GET_CLASS(obj) \
|
|
OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
|
|
|
|
typedef struct ARMGICClass {
|
|
ARMGICCommonClass parent_class;
|
|
int (*parent_init)(SysBusDevice *dev);
|
|
} ARMGICClass;
|
|
|
|
#endif /* !QEMU_ARM_GIC_INTERNAL_H */
|