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1e8cae4dfe
Rearrange the GIC and NVIC so both are straightforward subclasses of a common class, rather than having the NVIC source file textually include arm_gic.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
185 lines
5.8 KiB
C
185 lines
5.8 KiB
C
/*
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* ARM GIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "arm_gic_internal.h"
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static void gic_save(QEMUFile *f, void *opaque)
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{
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gic_state *s = (gic_state *)opaque;
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int i;
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int j;
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qemu_put_be32(f, s->enabled);
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for (i = 0; i < s->num_cpu; i++) {
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qemu_put_be32(f, s->cpu_enabled[i]);
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for (j = 0; j < GIC_INTERNAL; j++) {
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qemu_put_be32(f, s->priority1[j][i]);
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}
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for (j = 0; j < s->num_irq; j++) {
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qemu_put_be32(f, s->last_active[j][i]);
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}
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qemu_put_be32(f, s->priority_mask[i]);
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qemu_put_be32(f, s->running_irq[i]);
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qemu_put_be32(f, s->running_priority[i]);
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qemu_put_be32(f, s->current_pending[i]);
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}
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for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
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qemu_put_be32(f, s->priority2[i]);
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}
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for (i = 0; i < s->num_irq; i++) {
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qemu_put_be32(f, s->irq_target[i]);
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qemu_put_byte(f, s->irq_state[i].enabled);
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qemu_put_byte(f, s->irq_state[i].pending);
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qemu_put_byte(f, s->irq_state[i].active);
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qemu_put_byte(f, s->irq_state[i].level);
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qemu_put_byte(f, s->irq_state[i].model);
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qemu_put_byte(f, s->irq_state[i].trigger);
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}
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}
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static int gic_load(QEMUFile *f, void *opaque, int version_id)
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{
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gic_state *s = (gic_state *)opaque;
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int i;
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int j;
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if (version_id != 3) {
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return -EINVAL;
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}
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s->enabled = qemu_get_be32(f);
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for (i = 0; i < s->num_cpu; i++) {
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s->cpu_enabled[i] = qemu_get_be32(f);
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for (j = 0; j < GIC_INTERNAL; j++) {
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s->priority1[j][i] = qemu_get_be32(f);
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}
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for (j = 0; j < s->num_irq; j++) {
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s->last_active[j][i] = qemu_get_be32(f);
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}
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s->priority_mask[i] = qemu_get_be32(f);
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s->running_irq[i] = qemu_get_be32(f);
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s->running_priority[i] = qemu_get_be32(f);
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s->current_pending[i] = qemu_get_be32(f);
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}
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for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
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s->priority2[i] = qemu_get_be32(f);
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}
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for (i = 0; i < s->num_irq; i++) {
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s->irq_target[i] = qemu_get_be32(f);
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s->irq_state[i].enabled = qemu_get_byte(f);
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s->irq_state[i].pending = qemu_get_byte(f);
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s->irq_state[i].active = qemu_get_byte(f);
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s->irq_state[i].level = qemu_get_byte(f);
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s->irq_state[i].model = qemu_get_byte(f);
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s->irq_state[i].trigger = qemu_get_byte(f);
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}
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return 0;
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}
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static int arm_gic_common_init(SysBusDevice *dev)
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{
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gic_state *s = FROM_SYSBUS(gic_state, dev);
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int num_irq = s->num_irq;
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if (s->num_cpu > NCPU) {
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hw_error("requested %u CPUs exceeds GIC maximum %d\n",
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s->num_cpu, NCPU);
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}
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s->num_irq += GIC_BASE_IRQ;
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if (s->num_irq > GIC_MAXIRQ) {
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hw_error("requested %u interrupt lines exceeds GIC maximum %d\n",
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num_irq, GIC_MAXIRQ);
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}
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/* ITLinesNumber is represented as (N / 32) - 1 (see
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* gic_dist_readb) so this is an implementation imposed
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* restriction, not an architectural one:
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*/
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if (s->num_irq < 32 || (s->num_irq % 32)) {
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hw_error("%d interrupt lines unsupported: not divisible by 32\n",
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num_irq);
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}
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register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s);
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return 0;
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}
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static void arm_gic_common_reset(DeviceState *dev)
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{
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gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev));
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int i;
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memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < s->num_cpu; i++) {
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s->priority_mask[i] = 0xf0;
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s->current_pending[i] = 1023;
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s->running_irq[i] = 1023;
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s->running_priority[i] = 0x100;
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s->cpu_enabled[i] = 0;
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}
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for (i = 0; i < 16; i++) {
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GIC_SET_ENABLED(i, ALL_CPU_MASK);
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GIC_SET_TRIGGER(i);
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}
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if (s->num_cpu == 1) {
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/* For uniprocessor GICs all interrupts always target the sole CPU */
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for (i = 0; i < GIC_MAXIRQ; i++) {
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s->irq_target[i] = 1;
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}
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}
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s->enabled = 0;
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}
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static Property arm_gic_common_properties[] = {
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DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
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DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
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/* Revision can be 1 or 2 for GIC architecture specification
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* versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
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* (Internally, 0xffffffff also indicates "not a GIC but an NVIC".)
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*/
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DEFINE_PROP_UINT32("revision", gic_state, revision, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void arm_gic_common_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = arm_gic_common_reset;
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dc->props = arm_gic_common_properties;
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dc->no_user = 1;
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sc->init = arm_gic_common_init;
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}
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static TypeInfo arm_gic_common_type = {
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.name = TYPE_ARM_GIC_COMMON,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(gic_state),
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.class_size = sizeof(ARMGICCommonClass),
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.class_init = arm_gic_common_class_init,
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.abstract = true,
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};
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static void register_types(void)
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{
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type_register_static(&arm_gic_common_type);
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}
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type_init(register_types)
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