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94d1991445
Implement registers for clearing OBIO and PCI interrupts Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
543 lines
16 KiB
C
543 lines
16 KiB
C
/*
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* QEMU Ultrasparc APB PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* XXX This file and most of its contents are somewhat misnamed. The
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Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is
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the secondary PCI bridge. */
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#include "sysbus.h"
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#include "pci.h"
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#include "pci_host.h"
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#include "pci_bridge.h"
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#include "pci_internals.h"
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#include "apb_pci.h"
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#include "sysemu.h"
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#include "exec-memory.h"
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/* debug APB */
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//#define DEBUG_APB
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#ifdef DEBUG_APB
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#define APB_DPRINTF(fmt, ...) \
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do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define APB_DPRINTF(fmt, ...)
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#endif
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/*
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* Chipset docs:
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* PBM: "UltraSPARC IIi User's Manual",
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* http://www.sun.com/processors/manuals/805-0087.pdf
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*
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* APB: "Advanced PCI Bridge (APB) User's Manual",
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* http://www.sun.com/processors/manuals/805-1251.pdf
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*/
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#define PBM_PCI_IMR_MASK 0x7fffffff
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#define PBM_PCI_IMR_ENABLED 0x80000000
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#define POR (1 << 31)
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#define SOFT_POR (1 << 30)
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#define SOFT_XIR (1 << 29)
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#define BTN_POR (1 << 28)
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#define BTN_XIR (1 << 27)
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#define RESET_MASK 0xf8000000
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#define RESET_WCMASK 0x98000000
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#define RESET_WMASK 0x60000000
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#define MAX_IVEC 0x30
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typedef struct APBState {
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SysBusDevice busdev;
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PCIBus *bus;
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MemoryRegion apb_config;
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MemoryRegion pci_config;
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MemoryRegion pci_mmio;
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MemoryRegion pci_ioport;
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uint32_t iommu[4];
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uint32_t pci_control[16];
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uint32_t pci_irq_map[8];
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uint32_t obio_irq_map[32];
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qemu_irq *pbm_irqs;
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qemu_irq *ivec_irqs;
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uint32_t reset_control;
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unsigned int nr_resets;
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} APBState;
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static void pci_apb_set_irq(void *opaque, int irq_num, int level);
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static void apb_config_writel (void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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APBState *s = opaque;
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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s->iommu[(addr & 0xf) >> 2] = val;
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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s->pci_irq_map[(addr & 0x3f) >> 3] &= PBM_PCI_IMR_MASK;
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s->pci_irq_map[(addr & 0x3f) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */
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if (addr & 4) {
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s->obio_irq_map[(addr & 0xff) >> 3] &= PBM_PCI_IMR_MASK;
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s->obio_irq_map[(addr & 0xff) >> 3] |= val & ~PBM_PCI_IMR_MASK;
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}
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break;
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case 0x1400 ... 0x143f: /* PCI interrupt clear */
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if (addr & 4) {
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pci_apb_set_irq(s, (addr & 0x3f) >> 3, 0);
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}
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break;
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case 0x1800 ... 0x1860: /* OBIO interrupt clear */
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if (addr & 4) {
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pci_apb_set_irq(s, 0x20 | ((addr & 0xff) >> 3), 0);
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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s->pci_control[(addr & 0x3f) >> 2] = val;
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val &= RESET_MASK;
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s->reset_control &= ~(val & RESET_WCMASK);
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s->reset_control |= val & RESET_WMASK;
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if (val & SOFT_POR) {
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s->nr_resets = 0;
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qemu_system_reset_request();
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} else if (val & SOFT_XIR) {
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qemu_system_reset_request();
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}
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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break;
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}
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}
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static uint64_t apb_config_readl (void *opaque,
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target_phys_addr_t addr, unsigned size)
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{
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APBState *s = opaque;
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uint32_t val;
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switch (addr & 0xffff) {
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case 0x30 ... 0x4f: /* DMA error registers */
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val = 0;
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/* XXX: not implemented yet */
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break;
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case 0x200 ... 0x20b: /* IOMMU */
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val = s->iommu[(addr & 0xf) >> 2];
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break;
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case 0x20c ... 0x3ff: /* IOMMU flush */
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val = 0;
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break;
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case 0xc00 ... 0xc3f: /* PCI interrupt control */
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if (addr & 4) {
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val = s->pci_irq_map[(addr & 0x3f) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x1000 ... 0x1080: /* OBIO interrupt control */
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if (addr & 4) {
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val = s->obio_irq_map[(addr & 0xff) >> 3];
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} else {
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val = 0;
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}
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break;
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case 0x2000 ... 0x202f: /* PCI control */
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val = s->pci_control[(addr & 0x3f) >> 2];
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break;
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case 0xf020 ... 0xf027: /* Reset control */
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if (addr & 4) {
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val = s->reset_control;
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} else {
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val = 0;
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}
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break;
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case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */
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case 0xa400 ... 0xa67f: /* IOMMU diagnostics */
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case 0xa800 ... 0xa80f: /* Interrupt diagnostics */
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case 0xf000 ... 0xf01f: /* FFB config, memory control */
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/* we don't care */
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default:
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val = 0;
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break;
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}
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, val);
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return val;
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}
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static const MemoryRegionOps apb_config_ops = {
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.read = apb_config_readl,
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.write = apb_config_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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APBState *s = opaque;
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val = qemu_bswap_len(val, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %" PRIx64 "\n", __func__, addr, val);
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pci_data_write(s->bus, addr, val, size);
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}
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static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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uint32_t ret;
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APBState *s = opaque;
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ret = pci_data_read(s->bus, addr, size);
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ret = qemu_bswap_len(ret, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
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return ret;
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}
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static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outb(addr & IOPORTS_MASK, val);
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}
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static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outw(addr & IOPORTS_MASK, bswap16(val));
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}
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static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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cpu_outl(addr & IOPORTS_MASK, bswap32(val));
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}
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static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = cpu_inb(addr & IOPORTS_MASK);
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return val;
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}
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static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = bswap16(cpu_inw(addr & IOPORTS_MASK));
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return val;
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}
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static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
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{
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uint32_t val;
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val = bswap32(cpu_inl(addr & IOPORTS_MASK));
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return val;
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}
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static const MemoryRegionOps pci_ioport_ops = {
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.old_mmio = {
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.read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
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.write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/* The APB host has an IRQ line for each IRQ line of each slot. */
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static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
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}
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static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int bus_offset;
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if (pci_dev->devfn & 1)
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bus_offset = 16;
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else
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bus_offset = 0;
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return bus_offset + irq_num;
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}
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static void pci_apb_set_irq(void *opaque, int irq_num, int level)
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{
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APBState *s = opaque;
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/* PCI IRQ map onto the first 32 INO. */
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if (irq_num < 32) {
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if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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}
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} else {
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/* OBIO IRQ map onto the next 16 INO. */
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if (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED) {
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APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level);
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qemu_set_irq(s->ivec_irqs[irq_num], level);
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} else {
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APB_DPRINTF("%s: not enabled: lower irq %d\n", __func__, irq_num);
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qemu_irq_lower(s->ivec_irqs[irq_num]);
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}
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}
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}
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static int apb_pci_bridge_initfn(PCIDevice *dev)
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{
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int rc;
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rc = pci_bridge_initfn(dev);
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if (rc < 0) {
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return rc;
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}
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/*
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* command register:
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* According to PCI bridge spec, after reset
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* bus master bit is off
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* memory space enable bit is off
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* According to manual (805-1251.pdf).
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* the reset value should be zero unless the boot pin is tied high
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* (which is true) and thus it should be PCI_COMMAND_MEMORY.
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*/
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pci_set_word(dev->config + PCI_COMMAND,
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PCI_COMMAND_MEMORY);
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pci_set_word(dev->config + PCI_STATUS,
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PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
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PCI_STATUS_DEVSEL_MEDIUM);
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return 0;
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}
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PCIBus *pci_apb_init(target_phys_addr_t special_base,
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target_phys_addr_t mem_base,
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qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
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qemu_irq **pbm_irqs)
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{
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DeviceState *dev;
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SysBusDevice *s;
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APBState *d;
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PCIDevice *pci_dev;
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PCIBridge *br;
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/* Ultrasparc PBM main bus */
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dev = qdev_create(NULL, "pbm");
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qdev_init_nofail(dev);
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s = sysbus_from_qdev(dev);
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/* apb_config */
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sysbus_mmio_map(s, 0, special_base);
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/* PCI configuration space */
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sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
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/* pci_ioport */
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sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
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d = FROM_SYSBUS(APBState, s);
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memory_region_init(&d->pci_mmio, "pci-mmio", 0x100000000ULL);
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memory_region_add_subregion(get_system_memory(), mem_base, &d->pci_mmio);
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d->bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_apb_set_irq, pci_pbm_map_irq, d,
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&d->pci_mmio,
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get_system_io(),
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0, 32);
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*pbm_irqs = d->pbm_irqs;
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d->ivec_irqs = ivec_irqs;
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pci_create_simple(d->bus, 0, "pbm-pci");
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/* APB secondary busses */
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pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
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"pbm-bridge");
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
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pci_apb_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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*bus2 = pci_bridge_get_sec_bus(br);
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pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
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"pbm-bridge");
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br = DO_UPCAST(PCIBridge, dev, pci_dev);
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pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
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pci_apb_map_irq);
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qdev_init_nofail(&pci_dev->qdev);
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*bus3 = pci_bridge_get_sec_bus(br);
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return d->bus;
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}
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static void pci_pbm_reset(DeviceState *d)
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{
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unsigned int i;
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APBState *s = container_of(d, APBState, busdev.qdev);
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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for (i = 0; i < 32; i++) {
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s->obio_irq_map[i] &= PBM_PCI_IMR_MASK;
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}
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if (s->nr_resets++ == 0) {
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/* Power on reset */
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s->reset_control = POR;
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}
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}
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static const MemoryRegionOps pci_config_ops = {
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.read = apb_pci_config_read,
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.write = apb_pci_config_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int pci_pbm_init_device(SysBusDevice *dev)
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{
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APBState *s;
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unsigned int i;
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s = FROM_SYSBUS(APBState, dev);
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for (i = 0; i < 8; i++) {
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s->pci_irq_map[i] = (0x1f << 6) | (i << 2);
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}
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for (i = 0; i < 32; i++) {
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s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i;
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}
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s->pbm_irqs = qemu_allocate_irqs(pci_apb_set_irq, s, MAX_IVEC);
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/* apb_config */
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memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config",
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0x10000);
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/* at region 0 */
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sysbus_init_mmio(dev, &s->apb_config);
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memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config",
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0x1000000);
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/* at region 1 */
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sysbus_init_mmio(dev, &s->pci_config);
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/* pci_ioport */
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memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s,
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"apb-pci-ioport", 0x10000);
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/* at region 2 */
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sysbus_init_mmio(dev, &s->pci_ioport);
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return 0;
|
|
}
|
|
|
|
static int pbm_pci_host_init(PCIDevice *d)
|
|
{
|
|
pci_set_word(d->config + PCI_COMMAND,
|
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
|
pci_set_word(d->config + PCI_STATUS,
|
|
PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
return 0;
|
|
}
|
|
|
|
static void pbm_pci_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->init = pbm_pci_host_init;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_SABRE;
|
|
k->class_id = PCI_CLASS_BRIDGE_HOST;
|
|
}
|
|
|
|
static TypeInfo pbm_pci_host_info = {
|
|
.name = "pbm-pci",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PCIDevice),
|
|
.class_init = pbm_pci_host_class_init,
|
|
};
|
|
|
|
static void pbm_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = pci_pbm_init_device;
|
|
dc->reset = pci_pbm_reset;
|
|
}
|
|
|
|
static TypeInfo pbm_host_info = {
|
|
.name = "pbm",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(APBState),
|
|
.class_init = pbm_host_class_init,
|
|
};
|
|
|
|
static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
k->init = apb_pci_bridge_initfn;
|
|
k->exit = pci_bridge_exitfn;
|
|
k->vendor_id = PCI_VENDOR_ID_SUN;
|
|
k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
|
|
k->revision = 0x11;
|
|
k->config_write = pci_bridge_write_config;
|
|
k->is_bridge = 1;
|
|
dc->reset = pci_bridge_reset;
|
|
dc->vmsd = &vmstate_pci_device;
|
|
}
|
|
|
|
static TypeInfo pbm_pci_bridge_info = {
|
|
.name = "pbm-bridge",
|
|
.parent = TYPE_PCI_DEVICE,
|
|
.instance_size = sizeof(PCIBridge),
|
|
.class_init = pbm_pci_bridge_class_init,
|
|
};
|
|
|
|
static void pbm_register_types(void)
|
|
{
|
|
type_register_static(&pbm_host_info);
|
|
type_register_static(&pbm_pci_host_info);
|
|
type_register_static(&pbm_pci_bridge_info);
|
|
}
|
|
|
|
type_init(pbm_register_types)
|