Max Filippov 9ed7ae12af target-xtensa: implement LSCX and LSCI groups ... These are load/store instructions for FP registers with immediate or register index and optional base post-update. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>		2012-09-22 17:59:12 +00:00
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core-dc232b	target-xtensa: add dc232b core	2011-10-16 10:40:02 +00:00
core-dc233c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf	target-xtensa: add fsf core	2011-10-16 10:40:16 +00:00
core-dc232b.c	target-xtensa: add license to core-dc232b.c	2012-04-15 17:43:28 +00:00
core-dc233c.c	target-xtensa: add dc233c core	2012-04-15 17:43:16 +00:00
core-fsf.c	target-xtensa: add license to core-fsf.c	2012-04-15 17:43:43 +00:00
cpu-qom.h	target-xtensa: QOM'ify CPU	2012-04-14 03:48:08 +04:00
cpu.c	target-xtensa: Let cpu_xtensa_init() return XtensaCPU	2012-06-04 23:00:41 +02:00
cpu.h	target-xtensa: add FP registers	2012-09-22 17:59:12 +00:00
helper.c	target-xtensa: drop usage of prev_debug_excp_handler	2012-06-25 15:35:03 +02:00
helper.h	target-xtensa: add FP registers	2012-09-22 17:59:12 +00:00
machine.c	target-xtensa: add target stubs	2011-09-10 16:57:36 +00:00
Makefile.objs	target-xtensa: switch to AREG0-free mode	2012-06-10 20:09:22 +00:00
op_helper.c	target-xtensa: add FP registers	2012-09-22 17:59:12 +00:00
overlay_tool.h	target-xtensa: handle boolean option in overlays	2012-09-22 17:59:12 +00:00
translate.c	target-xtensa: implement LSCX and LSCI groups	2012-09-22 17:59:12 +00:00
xtensa-semi.c	target-xtensa: fix missing errno codes for mingw32	2012-09-08 08:46:29 +00:00