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qemu/target-tricore
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Bastian Koppelmann 0953225588 target-tricore: Add instructions of RRR opcode format 
Add microcode generator function gen_cond_sub.

Add helper functions:
    * ixmax/ixmin: search for the max/min value and its related index in a
                   vector of 16-bit values.
    * pack: dack two data registers into an IEEE-754 single precision floating
            point format number.
    * dvadj: divide-adjust the result after dvstep instructions.
    * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.

OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-01-27 11:48:02 +00:00
..
cpu-qom.h target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
cpu.c target-tricore: Several translator and cpu model fixes 2015-01-26 19:56:45 +00:00
cpu.h target-tricore: Fix bugs found by coverity 2015-01-26 19:56:45 +00:00
csfr.def target-tricore: Fix new typos 2015-01-15 10:44:13 +03:00
helper.c target-tricore: Remove the dummy interrupt boilerplate 2014-09-25 18:54:22 +01:00
helper.h target-tricore: Add instructions of RRR opcode format 2015-01-27 11:48:02 +00:00
Makefile.objs target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
op_helper.c target-tricore: Add instructions of RRR opcode format 2015-01-27 11:48:02 +00:00
translate.c target-tricore: Add instructions of RRR opcode format 2015-01-27 11:48:02 +00:00
tricore-defs.h target-tricore: Add target stubs and qom-cpu 2014-09-01 14:49:20 +01:00
tricore-opcodes.h target-tricore: Add instructions of RRR opcode format 2015-01-27 11:48:02 +00:00